modelsim.ini

TMS3205402Verilog HDL源码

[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3e = $MODEL_TECH/../actel/vhdl/proasic3e
syncad_vhdl_lib = C:\Libero\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
IterationLimit = 5000