top.lpc

TMS3205402Verilog HDL源码

#
#
# Constraint priority in your .ucf file is as follows:
#
#    highest 1.  Timing Ignore (TIG)
#            2.  FROM : THRU : TO specs
#            3.  FROM : TO specs
#    lowest  4.  PERIOD specs
#
# See the on-line "Library Reference Guide" document for
# additional timespec features and more information.
#
#
############################################################
#                                                                               
                                     #
#         LOCATION and ATTRIBUTE SPECIFICATIONS            #
#                                                                               
                                     #
############################################################
# Pin and CLB location locking constraints                 #
############################################################
#
# -----------------------
# Assign an IO pin number
# -----------------------
#INST io_buf_instance_name  LOC = P110 ;
#NET io_net_name  LOC = P111 ;
#
# -----------------------
# Assign a signal to a range of I/O pins
# -----------------------
#NET "signal_name" LOC=P32, P33, P34;
#
# -----------------------
# Place a logic element(called a BEL) in a specific CLB location.
# BEL = FF, LUT, RAM, etc...
# -----------------------
#INST instance_path/BEL_inst_name  LOC = CLB_R17C36 ;
#
# -----------------------
# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;
#
# -----------------------
# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1* LOC=clb_r1c1:clb_r5c7;
#
# -----------------------
# Prohibit IO pin P26 or CLBR5C3 from being used:
# -----------------------
#CONFIG PROHIBIT = P26 ;
#CONFIG PROHIBIT = CLB_R5C3 ;
# Config Prohibit is very important for forcing the software to not use critical
# configuration pins like INIT or DOUT on the FPGA.  The Mode pins and JTAG
# Pins require a special pad so they will not be available to this constraint
#
# -----------------------
# Assign an OBUF to be FAST or SLOW:
# -----------------------
#INST obuf_instance_name FAST ;
#INST obuf_instance_name SLOW ;
#
# -----------------------
# FPGAs only:  IOB input Flip-flop delay specification
# -----------------------
# Declare an IOB input FF delay (default = MAXDELAY).
# NOTE:  MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
# into an IOB by the "map -pr i" option.
#INST input_ff_instance_name MEDDELAY ;
#INST input_ff_instance_name NODELAY ;
#
# -----------------------
# Assign Global Clock Buffers Lower Left Right Side
# -----------------------
# INST gbuf1 LOC=SSW
#
# #
NET "A<0>" LOC = "P35";
NET "A<1>" LOC = "P34";
NET "A<2>" LOC = "P33";
NET "A<3>" LOC = "P31";
NET "CPLD_RESET" LOC = "P143";
NET "DRAM_CE" LOC = "P68";
NET "DRAM_RD" LOC = "P76";
NET "DRAM_WE" LOC = "P66";
NET "DS" LOC = "P16";
NET "D<0>" LOC = "P57";
NET "D<1>" LOC = "P56";
NET "D<2>" LOC = "P54";
NET "D<3>" LOC = "P53";
NET "D<4>" LOC = "P52";
NET "D<5>" LOC = "P51";
NET "D<6>" LOC = "P50";
NET "D<7>" LOC = "P49";
NET "D<8>" LOC = "P48";
NET "D<9>" LOC = "P46";
NET "D<10>" LOC = "P45";
NET "D<11>" LOC = "P44";
NET "D<12>" LOC = "P43";
NET "D<13>" LOC = "P41";
NET "D<14>" LOC = "P40";
NET "D<15>" LOC = "P39";
NET "EA<15>" LOC = "P22";
NET "EA<16>" LOC = "P21";
NET "EA<17>" LOC = "P19";
NET "EA<18>" LOC = "P20";
NET "FLASH_CE" LOC = "P61";
NET "FLASH_RD" LOC = "P60";
NET "FLASH_WE" LOC = "P64";
NET "IOSTRB" LOC = "P12";
NET "IS" LOC = "P15";
NET "MSTRB" LOC = "P13";
NET "PRAM_CE" LOC = "P70";
NET "PRAM_RD" LOC = "P71";
NET "PRAM_WE" LOC = "P69";
NET "PS" LOC = "P17";
NET "RW" LOC = "P14";
NET "A<4>" LOC = "P28";
NET "A14" LOC = "P58";
NET "A15" LOC = "P59";
NET "IDE_A<0>" LOC = "P30";
NET "IDE_A<1>" LOC = "P140";
NET "IDE_A<2>" LOC = "P142";
NET "IDE_A<3>" LOC = "P133";
NET "IDE_D<0>" LOC = "P132";
NET "IDE_D<1>" LOC = "P130";
NET "IDE_D<2>" LOC = "P128";
NET "IDE_D<3>" LOC = "P125";
NET "IDE_D<4>" LOC = "P121";
NET "IDE_D<5>" LOC = "P119";
NET "IDE_D<6>" LOC = "P117";
NET "IDE_D<7>" LOC = "P115";
NET "IDE_D<8>" LOC = "P113";
NET "IDE_D<9>" LOC = "P116";
NET "IDE_D<10>" LOC = "P118";
NET "IDE_D<11>" LOC = "P120";
NET "IDE_D<12>" LOC = "P124";
NET "IDE_D<13>" LOC = "P126";
NET "IDE_D<14>" LOC = "P129";
NET "IDE_D<15>" LOC = "P131";
NET "IDE_RD" LOC = "P135";
NET "IDE_WR" LOC = "P134";
NET "IDE0_CS0" LOC = "P5";
NET "IDE0_CS1" LOC = "P4";
NET "IDE1_CS0" LOC = "P3";
NET "IDE1_CS1" LOC = "P2";
NET "LED<0>" LOC = "P32";
NET "LED<1>" LOC = "139";

#PINLOCK_BEGIN

#Tue Aug 05 23:27:11 2003

NET "A14"            LOC =  "S:PIN58";
NET "A15"            LOC =  "S:PIN59";
NET "A<0>"           LOC =  "S:PIN35";
NET "A<1>"           LOC =  "S:PIN34";
NET "A<2>"           LOC =  "S:PIN33";
NET "A<3>"           LOC =  "S:PIN31";
NET "A<4>"           LOC =  "S:PIN28";
NET "CPLD_RESET"     LOC =  "S:PIN143";
NET "DS"             LOC =  "S:PIN16";
NET "IOSTRB"         LOC =  "S:PIN12";
NET "IS"             LOC =  "S:PIN15";
NET "MSTRB"          LOC =  "S:PIN13";
NET "PS"             LOC =  "S:PIN17";
NET "RW"             LOC =  "S:PIN14";
NET "IDE_A<0>"       LOC =  "S:PIN30";
NET "IDE_A<1>"       LOC =  "S:PIN140";
NET "IDE_A<2>"       LOC =  "S:PIN142";
NET "IDE_A<3>"       LOC =  "S:PIN133";
NET "D<0>"           LOC =  "S:PIN57";
NET "D<10>"          LOC =  "S:PIN45";
NET "D<11>"          LOC =  "S:PIN44";
NET "D<12>"          LOC =  "S:PIN43";
NET "D<13>"          LOC =  "S:PIN41";
NET "D<14>"          LOC =  "S:PIN40";
NET "D<1>"           LOC =  "S:PIN56";
NET "D<2>"           LOC =  "S:PIN54";
NET "D<3>"           LOC =  "S:PIN53";
NET "D<4>"           LOC =  "S:PIN52";
NET "D<5>"           LOC =  "S:PIN51";
NET "D<6>"           LOC =  "S:PIN50";
NET "D<7>"           LOC =  "S:PIN49";
NET "D<8>"           LOC =  "S:PIN48";
NET "D<9>"           LOC =  "S:PIN46";
NET "DRAM_CE"        LOC =  "S:PIN68";
NET "FLASH_RD"       LOC =  "S:PIN60";
NET "DRAM_RD"        LOC =  "S:PIN76";
NET "PRAM_RD"        LOC =  "S:PIN71";
NET "FLASH_WE"       LOC =  "S:PIN64";
NET "DRAM_WE"        LOC =  "S:PIN66";
NET "PRAM_WE"        LOC =  "S:PIN69";
NET "D<15>"          LOC =  "S:PIN39";
NET "EA<15>"         LOC =  "S:PIN22";
NET "EA<16>"         LOC =  "S:PIN21";
NET "EA<17>"         LOC =  "S:PIN19";
NET "EA<18>"         LOC =  "S:PIN20";
NET "FLASH_CE"       LOC =  "S:PIN61";
NET "IDE0_CS0"       LOC =  "S:PIN5";
NET "IDE0_CS1"       LOC =  "S:PIN4";
NET "IDE1_CS0"       LOC =  "S:PIN3";
NET "IDE1_CS1"       LOC =  "S:PIN2";
NET "IDE_D<0>"       LOC =  "S:PIN132";
NET "IDE_D<10>"      LOC =  "S:PIN118";
NET "IDE_D<11>"      LOC =  "S:PIN120";
NET "IDE_D<12>"      LOC =  "S:PIN124";
NET "IDE_D<13>"      LOC =  "S:PIN126";
NET "IDE_D<14>"      LOC =  "S:PIN129";
NET "IDE_D<15>"      LOC =  "S:PIN131";
NET "IDE_D<1>"       LOC =  "S:PIN130";
NET "IDE_D<2>"       LOC =  "S:PIN128";
NET "IDE_D<3>"       LOC =  "S:PIN125";
NET "IDE_D<4>"       LOC =  "S:PIN121";
NET "IDE_D<5>"       LOC =  "S:PIN119";
NET "IDE_D<6>"       LOC =  "S:PIN117";
NET "IDE_D<7>"       LOC =  "S:PIN115";
NET "IDE_D<8>"       LOC =  "S:PIN113";
NET "IDE_D<9>"       LOC =  "S:PIN116";
NET "IDE_RD"         LOC =  "S:PIN135";
NET "IDE_WR"         LOC =  "S:PIN134";
NET "LED<0>"         LOC =  "S:PIN32";
NET "LED<1>"         LOC =  "S:PIN139";
NET "PRAM_CE"        LOC =  "S:PIN70";
#PINLOCK_END