📄 mc8051_p.vhd
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--------------------------------------------------------------------------------- ---- X X XXXXXX XXXXXX XXXXXX XXXXXX X ---- XX XX X X X X X X X XX ---- X X X X X X X X X X X X ---- X X X X X X X X X X X X ---- X X X X XXXXXX X X XXXXXX X ---- X X X X X X X X X ---- X X X X X X X X X ---- X X X X X X X X X X ---- X X XXXXXX XXXXXX XXXXXX XXXXXX X ---- ---- ---- O R E G A N O S Y S T E M S ---- ---- Design & Consulting ---- ----------------------------------------------------------------------------------- ---- Web: http://www.oregano.at/ ---- ---- Contact: mc8051@oregano.at ---- ----------------------------------------------------------------------------------- ---- MC8051 - VHDL 8051 Microcontroller IP Core ---- Copyright (C) 2001 OREGANO SYSTEMS ---- ---- This library is free software; you can redistribute it and/or ---- modify it under the terms of the GNU Lesser General Public ---- License as published by the Free Software Foundation; either ---- version 2.1 of the License, or (at your option) any later version. ---- ---- This library is distributed in the hope that it will be useful, ---- but WITHOUT ANY WARRANTY; without even the implied warranty of ---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ---- Lesser General Public License for more details. ---- ---- Full details of the license can be found in the file LGPL.TXT. ---- ---- You should have received a copy of the GNU Lesser General Public ---- License along with this library; if not, write to the Free Software ---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ---- --------------------------------------------------------------------------------------- Author: Roland H鰈ler---- Filename: mc8051_p.vhd---- Date of Creation: Mon Aug 9 12:14:48 1999---- Version: $Revision: 1.14 $---- Date of Latest Version: $Date: 2002/01/07 12:17:45 $------ Description: Collection of constants, types, and components.---------------------------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package mc8051_p is ----------------------------------------------------------------------------- -- Set data width of mc8051_alu (no other than 8 supported at the moment!) -- Default: 8 constant C_DWIDTH : integer := 8; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Select whether to implement (1) or skip (0) the multiplier -- Default: 1 constant C_IMPL_MUL : integer := 1; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Select whether to implement (1) or skip (0) the divider -- Default: 1 constant C_IMPL_DIV : integer := 1; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Select whether to implement (1) or skip (0) the decimal adjustment command -- Default: 1 constant C_IMPL_DA : integer := 1; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Select how many timer/counter units should be implemented -- Default: 1 constant C_IMPL_N_TMR : integer := 1; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Select how many serial interface units should be implemented -- Default: C_IMPL_N_TMR ---(DO NOT CHANGE!)--- constant C_IMPL_N_SIU : integer := C_IMPL_N_TMR; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- -- Select how many external interrupt-inputs should be implemented -- Default: C_IMPL_N_TMR ---(DO NOT CHANGE!)--- constant C_IMPL_N_EXT : integer := C_IMPL_N_TMR; ----------------------------------------------------------------------------- constant OFF : std_logic_vector(5 downto 0) := "000000"; constant DA : std_logic_vector(5 downto 0) := "100000"; constant ADD_ACC_RAM : std_logic_vector(5 downto 0) := "100001"; constant ADD_ACC_ROM : std_logic_vector(5 downto 0) := "100010"; constant ADDC_ACC_RAM : std_logic_vector(5 downto 0) := "100011"; constant ADDC_ACC_ROM : std_logic_vector(5 downto 0) := "100100"; constant AND_ACC_RAM : std_logic_vector(5 downto 0) := "100101"; constant AND_ACC_ROM : std_logic_vector(5 downto 0) := "100110"; constant AND_RAM_ROM : std_logic_vector(5 downto 0) := "100111"; constant SUB_ACC_RAM : std_logic_vector(5 downto 0) := "101000"; constant SUB_ACC_ROM : std_logic_vector(5 downto 0) := "101001"; constant MUL_ACC_RAM : std_logic_vector(5 downto 0) := "101010"; constant DIV_ACC_RAM : std_logic_vector(5 downto 0) := "101011"; constant OR_RAM_ACC : std_logic_vector(5 downto 0) := "101100"; constant OR_ROM_ACC : std_logic_vector(5 downto 0) := "101101"; constant OR_ROM_RAM : std_logic_vector(5 downto 0) := "101110"; constant XOR_RAM_ACC : std_logic_vector(5 downto 0) := "101111"; constant XOR_ROM_ACC : std_logic_vector(5 downto 0) := "110000"; constant XOR_ROM_RAM : std_logic_vector(5 downto 0) := "110001"; constant RL_ACC : std_logic_vector(5 downto 0) := "110010"; constant RLC_ACC : std_logic_vector(5 downto 0) := "110011"; constant RR_ACC : std_logic_vector(5 downto 0) := "110100"; constant RRC_ACC : std_logic_vector(5 downto 0) := "110101"; constant INV_ACC : std_logic_vector(5 downto 0) := "110110"; constant INV_RAM : std_logic_vector(5 downto 0) := "110111"; constant DEC_ACC : std_logic_vector(5 downto 0) := "111000"; constant DEC_RAM : std_logic_vector(5 downto 0) := "111001"; constant COMP_RAM_ACC : std_logic_vector(5 downto 0) := "111010"; constant COMP_ROM_ACC : std_logic_vector(5 downto 0) := "111011"; constant COMP_ROM_RAM : std_logic_vector(5 downto 0) := "111100"; constant INC_ACC : std_logic_vector(5 downto 0) := "111110"; constant INC_RAM : std_logic_vector(5 downto 0) := "111111"; constant ACALL : std_logic_vector(4 downto 0) := "10001"; constant ADD_A_RR : std_logic_vector(4 downto 0) := "00101"; constant ADD_A_D : std_logic_vector(7 downto 0) := "00100101"; constant ADD_A_ATRI : std_logic_vector(6 downto 0) := "0010011"; constant ADD_A_DATA : std_logic_vector(7 downto 0) := "00100100"; constant ADDC_A_RR : std_logic_vector(4 downto 0) := "00111"; constant ADDC_A_D : std_logic_vector(7 downto 0) := "00110101"; constant ADDC_A_ATRI : std_logic_vector(6 downto 0) := "0011011"; constant ADDC_A_DATA : std_logic_vector(7 downto 0) := "00110100"; constant AJMP : std_logic_vector(4 downto 0) := "00001"; constant ANL_A_RR : std_logic_vector(4 downto 0) := "01011"; constant ANL_A_D : std_logic_vector(7 downto 0) := "01010101"; constant ANL_A_ATRI : std_logic_vector(6 downto 0) := "0101011"; constant ANL_A_DATA : std_logic_vector(7 downto 0) := "01010100"; constant ANL_D_A : std_logic_vector(7 downto 0) := "01010010"; constant ANL_D_DATA : std_logic_vector(7 downto 0) := "01010011"; constant ANL_C_BIT : std_logic_vector(7 downto 0) := "10000010"; constant ANL_C_NBIT : std_logic_vector(7 downto 0) := "10110000"; constant CJNE_A_D : std_logic_vector(7 downto 0) := "10110101"; constant CJNE_A_DATA : std_logic_vector(7 downto 0) := "10110100"; constant CJNE_RR_DATA : std_logic_vector(4 downto 0) := "10111"; constant CJNE_ATRI_DATA: std_logic_vector(6 downto 0) := "1011011" ; constant CLR_A : std_logic_vector(7 downto 0) := "11100100"; constant CLR_C : std_logic_vector(7 downto 0) := "11000011"; constant CLR_BIT : std_logic_vector(7 downto 0) := "11000010"; constant CPL_A : std_logic_vector(7 downto 0) := "11110100"; constant CPL_C : std_logic_vector(7 downto 0) := "10110011"; constant CPL_BIT : std_logic_vector(7 downto 0) := "10110010"; constant DA_A : std_logic_vector(7 downto 0) := "11010100"; constant DEC_A : std_logic_vector(7 downto 0) := "00010100"; constant DEC_RR : std_logic_vector(4 downto 0) := "00011"; constant DEC_D : std_logic_vector(7 downto 0) := "00010101"; constant DEC_ATRI : std_logic_vector(6 downto 0) := "0001011"; constant DIV_AB : std_logic_vector(7 downto 0) := "10000100"; constant DJNZ_RR : std_logic_vector(4 downto 0) := "11011"; constant DJNZ_D : std_logic_vector(7 downto 0) := "11010101"; constant INC_A : std_logic_vector(7 downto 0) := "00000100"; constant INC_RR : std_logic_vector(4 downto 0) := "00001"; constant INC_D : std_logic_vector(7 downto 0) := "00000101"; constant INC_ATRI : std_logic_vector(6 downto 0) := "0000011"; constant INC_DPTR : std_logic_vector(7 downto 0) := "10100011"; constant JB : std_logic_vector(7 downto 0) := "00100000"; constant JBC : std_logic_vector(7 downto 0) := "00010000"; constant JC : std_logic_vector(7 downto 0) := "01000000"; constant JMP_A_DPTR : std_logic_vector(7 downto 0) := "01110011"; constant JNB : std_logic_vector(7 downto 0) := "00110000"; constant JNC : std_logic_vector(7 downto 0) := "01010000"; constant JNZ : std_logic_vector(7 downto 0) := "01110000"; constant JZ : std_logic_vector(7 downto 0) := "01100000"; constant LCALL : std_logic_vector(7 downto 0) := "00010010"; constant LJMP : std_logic_vector(7 downto 0) := "00000010"; constant MOV_A_RR : std_logic_vector(4 downto 0) := "11101"; constant MOV_A_D : std_logic_vector(7 downto 0) := "11100101"; constant MOV_A_ATRI : std_logic_vector(6 downto 0) := "1110011"; constant MOV_A_DATA : std_logic_vector(7 downto 0) := "01110100"; constant MOV_RR_A : std_logic_vector(4 downto 0) := "11111"; constant MOV_RR_D : std_logic_vector(4 downto 0) := "10101"; constant MOV_RR_DATA : std_logic_vector(4 downto 0) := "01111"; constant MOV_D_A : std_logic_vector(7 downto 0) := "11110101"; constant MOV_D_RR : std_logic_vector(4 downto 0) := "10001"; constant MOV_D_D : std_logic_vector(7 downto 0) := "10000101"; constant MOV_D_ATRI : std_logic_vector(6 downto 0) := "1000011"; constant MOV_D_DATA : std_logic_vector(7 downto 0) := "01110101"; constant MOV_ATRI_A : std_logic_vector(6 downto 0) := "1111011"; constant MOV_ATRI_D : std_logic_vector(6 downto 0) := "1010011"; constant MOV_ATRI_DATA : std_logic_vector(6 downto 0) := "0111011"; constant MOVC_A_ATDPTR : std_logic_vector(7 downto 0) := "10010011"; constant MOVC_A_ATPC : std_logic_vector(7 downto 0) := "10000011"; constant MOVX_A_ATRI : std_logic_vector(6 downto 0) := "1110001"; constant MOVX_A_ATDPTR : std_logic_vector(7 downto 0) := "11100000"; constant MOVX_ATRI_A : std_logic_vector(6 downto 0) := "1111001"; constant MOVX_ATDPTR_A : std_logic_vector(7 downto 0) := "11110000"; constant MOV_C_BIT : std_logic_vector(7 downto 0) := "10100010"; constant MOV_BIT_C : std_logic_vector(7 downto 0) := "10010010"; constant MOV_DPTR_DATA : std_logic_vector(7 downto 0) := "10010000"; constant MUL_AB : std_logic_vector(7 downto 0) := "10100100"; constant NOP : std_logic_vector(7 downto 0) := "00000000"; constant ORL_A_RR : std_logic_vector(4 downto 0) := "01001"; constant ORL_A_D : std_logic_vector(7 downto 0) := "01000101"; constant ORL_A_ATRI : std_logic_vector(6 downto 0) := "0100011"; constant ORL_A_DATA : std_logic_vector(7 downto 0) := "01000100"; constant ORL_D_A : std_logic_vector(7 downto 0) := "01000010"; constant ORL_D_DATA : std_logic_vector(7 downto 0) := "01000011"; constant ORL_C_BIT : std_logic_vector(7 downto 0) := "01110010"; constant ORL_C_NBIT : std_logic_vector(7 downto 0) := "10100000"; constant POP : std_logic_vector(7 downto 0) := "11010000"; constant PUSH : std_logic_vector(7 downto 0) := "11000000"; constant RET : std_logic_vector(7 downto 0) := "00100010"; constant RETI : std_logic_vector(7 downto 0) := "00110010"; constant RL_A : std_logic_vector(7 downto 0) := "00100011"; constant RLC_A : std_logic_vector(7 downto 0) := "00110011"; constant RR_A : std_logic_vector(7 downto 0) := "00000011"; constant RRC_A : std_logic_vector(7 downto 0) := "00010011"; constant SETB_C : std_logic_vector(7 downto 0) := "11010011"; constant SETB_BIT : std_logic_vector(7 downto 0) := "11010010"; constant SJMP : std_logic_vector(7 downto 0) := "10000000"; constant SUBB_A_RR : std_logic_vector(4 downto 0) := "10011"; constant SUBB_A_D : std_logic_vector(7 downto 0) := "10010101"; constant SUBB_A_ATRI : std_logic_vector(6 downto 0) := "1001011"; constant SUBB_A_DATA : std_logic_vector(7 downto 0) := "10010100"; constant SWAP_A : std_logic_vector(7 downto 0) := "11000100"; constant XCH_A_RR : std_logic_vector(4 downto 0) := "11001"; constant XCH_A_D : std_logic_vector(7 downto 0) := "11000101"; constant XCH_A_ATRI : std_logic_vector(6 downto 0) := "1100011"; constant XCHD_A_ATRI : std_logic_vector(6 downto 0) := "1101011"; constant XRL_A_RR : std_logic_vector(4 downto 0) := "01101"; constant XRL_A_D : std_logic_vector(7 downto 0) := "01100101"; constant XRL_A_ATRI : std_logic_vector(6 downto 0) := "0110011"; constant XRL_A_DATA : std_logic_vector(7 downto 0) := "01100100"; constant XRL_D_A : std_logic_vector(7 downto 0) := "01100010"; constant XRL_D_DATA : std_logic_vector(7 downto 0) := "01100011"; type t_state is (STARTUP, FETCH, EXEC1, EXEC2, EXEC3); type t_instr_category is (IC_ACALL, IC_ADD_A_RR, IC_ADD_A_D, IC_ADD_A_ATRI, IC_ADD_A_DATA, IC_ADDC_A_RR, IC_ADDC_A_D, IC_ADDC_A_ATRI, IC_ADDC_A_DATA, IC_AJMP, IC_ANL_A_RR, IC_ANL_A_D, IC_ANL_A_ATRI, IC_ANL_A_DATA, IC_ANL_D_A, IC_ANL_D_DATA,⌨️ 快捷键说明
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