tb_mc8051_alu_sim.vhd

这是用C语言编写的关于8051的VHDL的源代码

              and (s_ovi = v_ovo)
              and (s_result = v_result)
              report "ERROR in " & IMAGE(DWIDTH) & "bit ADD operation!"
              severity failure;
          end if;
        end loop;  -- f
      end loop;  -- i
    end loop;  -- j  
    assert false
      report "********* " & IMAGE(DWIDTH)
      & "BIT ADD SEQUENCE FINISHED AT "
      & IMAGE(now) & " !" & " *********" 
      severity note;
    s_add_end <= true;
    wait;
  end PROC_ADD;
  -----------------------------------------------------------------------------
  
  -----------------------------------------------------------------------------
  --                                                                         --
  --  PROC_SUB - Test the logical SUB command                                --
  --                                                                         --
  --  Procedure to generate all the input data to test the                   --
  --  SUB command. Furthermore the results are compared with the             --
  --  expected values and the simulation is stopped with an error message    --
  --  if the test failes.                                                    --
  -----------------------------------------------------------------------------
  procedure PROC_SUB (
    constant DWIDTH     : in  positive;
    constant PROP_DELAY : in  time;
    signal   s_cyi      : in  std_logic_vector;
    signal   s_ovi      : in  std_logic;
    signal   s_result   : in  std_logic_vector;
    signal   s_cyo      : out std_logic_vector;
    signal   s_ovo      : out std_logic;
    signal   s_operanda : out std_logic_vector;
    signal   s_operandb : out std_logic_vector;
    signal   s_sub_end  : out boolean) is

    variable v_result : std_logic_vector(DWIDTH-1 downto 0);
    variable v_flags  : std_logic_vector((DWIDTH-1)/4+1 downto 0);
    variable v_cyo    : std_logic_vector(((DWIDTH-1)/4) downto 0);
    variable v_ovo    : std_logic;
    variable v_carry  : integer;

  begin
    s_sub_end <= false;
    for j in 0 to 2**DWIDTH-1 loop
      s_operanda <= conv_std_logic_vector(j,DWIDTH);
      for i in 0 to 2**DWIDTH-1 loop
        s_operandb <= conv_std_logic_vector(i,DWIDTH);
        for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
          v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
          s_cyo <= v_flags(((DWIDTH-1)/4) downto 0);
          s_ovo <= v_flags(v_flags'HIGH);
          v_carry := conv_integer(v_flags((DWIDTH-1)/4));
            for h in 0 to (DWIDTH-1)/4 loop
              if DWIDTH > (h+1)*4 then
                if (j mod 2**((h+1)*4) - i mod 2**((h+1)*4) - v_carry)
                  < 0 then 
                  v_cyo(h) := '1';                          
                else                                        
                  v_cyo(h) := '0';                          
                end if;
              else
                if (j mod 2**(DWIDTH) - i mod 2**(DWIDTH) - v_carry)
                  < 0 then
                  v_cyo(h) := '1';                          
                else                                        
                  v_cyo(h) := '0';                          
                end if;
              end if;
            end loop;  -- h
 --           if DWIDTH = 1 then
 --             v_ovo := '0';
 --           else
              if (j - i - v_carry < 0
                  and (j mod 2**(DWIDTH-1) - i mod 2**(DWIDTH-1) - v_carry)
                  >= 0) or 
                (j - i - v_carry >= 0
                 and (j mod 2**(DWIDTH-1) - i mod 2**(DWIDTH-1) - v_carry)
                 < 0) then
                v_ovo := '1';                               
              else                                          
                v_ovo := '0';                               
              end if;                                       
 --           end if;
            v_result := conv_std_logic_vector(j - i - v_carry,DWIDTH);
            wait for PROP_DELAY;
            assert (s_cyi = v_cyo)
              and (s_ovi = v_ovo)
              and (s_result = v_result)
              report "ERROR in " & IMAGE(DWIDTH) & "bit SUB operation!"
              severity failure;
        end loop;  -- f
      end loop;  -- i
    end loop;  -- j  
    assert false
      report "********* " & IMAGE(DWIDTH)
      & "BIT SUB SEQUENCE FINISHED AT "
      & IMAGE(now) & " !" & " *********" 
      severity note;
    s_sub_end <= true;
    wait;
  end PROC_SUB;
  -----------------------------------------------------------------------------

  constant PROP_DELAY : time := 100 ns;
  constant MAX_DWIDTH : integer := 11;

  type t_data_DA is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH-1 downto 0);
  type t_cmd_DA is array (1 to MAX_DWIDTH) of std_logic_vector(5 downto 0);
  type t_cy_DA is array (1 to MAX_DWIDTH) of
    std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
  type t_ov_DA is array (1 to MAX_DWIDTH) of std_logic;
  type t_end_DA is array (1 to MAX_DWIDTH) of boolean;
  
  type t_data_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH-1 downto 0);
  type t_cmd_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(5 downto 0);
  type t_ov_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of std_logic;
  type t_end_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of boolean;
  type t_cy_DIV_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector((MAX_DWIDTH-1)/4 downto 0);

  type t_product_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH*2-1 downto 0);
  type t_data_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH-1 downto 0);
  type t_cmd_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector(5 downto 0);
  type t_ov_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of std_logic;
  type t_end_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of boolean;
  type t_cy_MUL_ACC_RAM is array (1 to MAX_DWIDTH) of
    std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
  
  type t_data_STIM is array (1 to MAX_DWIDTH) of
    std_logic_vector(MAX_DWIDTH-1 downto 0);
  type t_cmd_STIM is array (1 to MAX_DWIDTH) of std_logic_vector(5 downto 0);
  type t_cy_STIM is array (1 to MAX_DWIDTH) of
    std_logic_vector((MAX_DWIDTH-1)/4 downto 0);
  type t_ov_STIM is array (1 to MAX_DWIDTH) of std_logic;
  type t_end_STIM is array (1 to MAX_DWIDTH) of boolean;

  type t_pass is array (1 to MAX_DWIDTH+1) of boolean;

  signal rom_data_DA : t_data_DA;
  signal ram_data_DA : t_data_DA;
  signal acc_DA : t_data_DA;
  signal hlp_DA : t_data_DA;
  signal cmd_DA : t_cmd_DA;
  signal cy_DA : t_cy_DA;
  signal ov_DA : t_ov_DA;
  signal new_cy_DA : t_cy_DA;
  signal new_ov_DA : t_ov_DA;
  signal result_a_DA : t_data_DA;
  signal result_b_DA : t_data_DA;
  signal end_DA : t_end_DA;

  signal rom_data_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal ram_data_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal acc_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal hlp_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal cmd_DIV_ACC_RAM : t_cmd_DIV_ACC_RAM;
  signal cy_DIV_ACC_RAM : t_cy_DIV_ACC_RAM;
  signal ov_DIV_ACC_RAM : t_ov_DIV_ACC_RAM;
  signal new_cy_DIV_ACC_RAM : t_cy_DIV_ACC_RAM;
  signal new_ov_DIV_ACC_RAM : t_ov_DIV_ACC_RAM;
  signal result_a_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal result_b_DIV_ACC_RAM : t_data_DIV_ACC_RAM;
  signal end_DIV_ACC_RAM : t_end_DIV_ACC_RAM;

  signal rom_data_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal ram_data_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal acc_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal hlp_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal cmd_MUL_ACC_RAM : t_cmd_MUL_ACC_RAM;
  signal cy_MUL_ACC_RAM : t_cy_MUL_ACC_RAM;
  signal ov_MUL_ACC_RAM : t_ov_MUL_ACC_RAM;
  signal new_cy_MUL_ACC_RAM : t_cy_MUL_ACC_RAM;
  signal new_ov_MUL_ACC_RAM : t_ov_MUL_ACC_RAM;
  signal result_a_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal result_b_MUL_ACC_RAM : t_data_MUL_ACC_RAM;
  signal product_MUL_ACC_RAM : t_product_MUL_ACC_RAM;
  signal end_MUL_ACC_RAM : t_end_MUL_ACC_RAM;

  signal rom_data_AND_ACC_RAM : t_data_STIM;
  signal ram_data_AND_ACC_RAM : t_data_STIM;
  signal acc_AND_ACC_RAM : t_data_STIM;
  signal hlp_AND_ACC_RAM : t_data_STIM;
  signal cmd_AND_ACC_RAM : t_cmd_STIM;
  signal cy_AND_ACC_RAM : t_cy_STIM;
  signal ov_AND_ACC_RAM : t_ov_STIM;
  signal new_cy_AND_ACC_RAM : t_cy_STIM;
  signal new_ov_AND_ACC_RAM : t_ov_STIM;
  signal result_a_AND_ACC_RAM : t_data_STIM;
  signal result_b_AND_ACC_RAM : t_data_STIM;
  signal end_AND_ACC_RAM : t_end_STIM;

  signal rom_data_OR_ACC_RAM : t_data_STIM;
  signal ram_data_OR_ACC_RAM : t_data_STIM;
  signal acc_OR_ACC_RAM : t_data_STIM;
  signal hlp_OR_ACC_RAM : t_data_STIM;
  signal cmd_OR_ACC_RAM : t_cmd_STIM;
  signal cy_OR_ACC_RAM : t_cy_STIM;
  signal ov_OR_ACC_RAM : t_ov_STIM;
  signal new_cy_OR_ACC_RAM : t_cy_STIM;
  signal new_ov_OR_ACC_RAM : t_ov_STIM;
  signal result_a_OR_ACC_RAM : t_data_STIM;
  signal result_b_OR_ACC_RAM : t_data_STIM;
  signal end_OR_ACC_RAM : t_end_STIM;

  signal rom_data_XOR_ACC_RAM : t_data_STIM;
  signal ram_data_XOR_ACC_RAM : t_data_STIM;
  signal acc_XOR_ACC_RAM : t_data_STIM;
  signal hlp_XOR_ACC_RAM : t_data_STIM;
  signal cmd_XOR_ACC_RAM : t_cmd_STIM;
  signal cy_XOR_ACC_RAM : t_cy_STIM;
  signal ov_XOR_ACC_RAM : t_ov_STIM;
  signal new_cy_XOR_ACC_RAM : t_cy_STIM;
  signal new_ov_XOR_ACC_RAM : t_ov_STIM;
  signal result_a_XOR_ACC_RAM : t_data_STIM;
  signal result_b_XOR_ACC_RAM : t_data_STIM;
  signal end_XOR_ACC_RAM : t_end_STIM;

  signal rom_data_ADD_ACC_RAM : t_data_STIM;
  signal ram_data_ADD_ACC_RAM : t_data_STIM;
  signal acc_ADD_ACC_RAM : t_data_STIM;
  signal hlp_ADD_ACC_RAM : t_data_STIM;
  signal cmd_ADD_ACC_RAM : t_cmd_STIM;
  signal cy_ADD_ACC_RAM : t_cy_STIM;
  signal ov_ADD_ACC_RAM : t_ov_STIM;
  signal new_cy_ADD_ACC_RAM : t_cy_STIM;
  signal new_ov_ADD_ACC_RAM : t_ov_STIM;
  signal result_a_ADD_ACC_RAM : t_data_STIM;
  signal result_b_ADD_ACC_RAM : t_data_STIM;
  signal end_ADD_ACC_RAM : t_end_STIM;
  
  signal rom_data_ADDC_ACC_RAM : t_data_STIM;
  signal ram_data_ADDC_ACC_RAM : t_data_STIM;
  signal acc_ADDC_ACC_RAM : t_data_STIM;
  signal hlp_ADDC_ACC_RAM : t_data_STIM;
  signal cmd_ADDC_ACC_RAM : t_cmd_STIM;
  signal cy_ADDC_ACC_RAM : t_cy_STIM;
  signal ov_ADDC_ACC_RAM : t_ov_STIM;
  signal new_cy_ADDC_ACC_RAM : t_cy_STIM;
  signal new_ov_ADDC_ACC_RAM : t_ov_STIM;
  signal result_a_ADDC_ACC_RAM : t_data_STIM;
  signal result_b_ADDC_ACC_RAM : t_data_STIM;
  signal end_ADDC_ACC_RAM : t_end_STIM;
  
  signal rom_data_SUB_ACC_RAM : t_data_STIM;
  signal ram_data_SUB_ACC_RAM : t_data_STIM;
  signal acc_SUB_ACC_RAM : t_data_STIM;
  signal hlp_SUB_ACC_RAM : t_data_STIM;
  signal cmd_SUB_ACC_RAM : t_cmd_STIM;
  signal cy_SUB_ACC_RAM : t_cy_STIM;
  signal ov_SUB_ACC_RAM : t_ov_STIM;
  signal new_cy_SUB_ACC_RAM : t_cy_STIM;
  signal new_ov_SUB_ACC_RAM : t_ov_STIM;
  signal result_a_SUB_ACC_RAM : t_data_STIM;
  signal result_b_SUB_ACC_RAM : t_data_STIM;
  signal end_SUB_ACC_RAM : t_end_STIM;

  signal pass : t_pass := (others => true);

begin

  -----------------------------------------------------------------------------
  -- Test the DA command for data widths from 1 up to MAX_DWIDTH             --
  -----------------------------------------------------------------------------
  gen_da: for i in 1 to MAX_DWIDTH generate
    -- Values which do not change during DA test
    rom_data_DA(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
    ram_data_DA(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
    hlp_DA(i)      <= conv_std_logic_vector(0,MAX_DWIDTH);
    cmd_DA(i)      <= conv_std_logic_vector(32,6);
    ov_DA(i)       <= '0';
    -- Instantiate the ALU unit with the data width set to i
    i_mc8051_alu_DA : mc8051_alu    
      generic map (                 
        DWIDTH => i)                
      port map (                    
        rom_data_i => rom_data_DA(i)(i-1 downto 0), 
        ram_data_i => ram_data_DA(i)(i-1 downto 0), 
        acc_i      => acc_DA(i)(i-1 downto 0),      
--        hlp_i      => hlp_DA(i)(i-1 downto 0),      
        cmd_i      => cmd_DA(i),      
        cy_i       => cy_DA(i)((i-1)/4 downto 0),       
        ov_i       => ov_DA(i),       
        new_cy_o   => new_cy_DA(i)((i-1)/4 downto 0),   
        new_ov_o   => new_ov_DA(i),   
        result_a_o => result_a_DA(i)(i-1 downto 0), 
        result_b_o => result_b_DA(i)(i-1 downto 0));
    -- Call the test procedure for the DA command
    PROC_DA (DWIDTH     => i,
             PROP_DELAY => PROP_DELAY,
             s_datao    => acc_DA(i)(i-1 downto 0),
             s_cy       => cy_DA(i)((i-1)/4 downto 0),
             s_datai    => result_a_DA(i)(i-1 downto 0),
             s_cyi      => new_cy_DA(i)((i-1)/4 downto 0),
             s_da_end   => end_DA(i));
  end generate GEN_DA;
  -----------------------------------------------------------------------------
  
  -----------------------------------------------------------------------------
  -- Test the DIV_ACC_RAM command for data widths from 1 up to MAX_DWIDTH    --
  -----------------------------------------------------------------------------
  gen_div_acc_ram: for i in 1 to MAX_DWIDTH generate
    -- Values which do not change during DIV_ACC_RAM test
    rom_data_DIV_ACC_RAM(i) <= conv_std_logic_vector(0,MAX_DWIDTH);
    hlp_DIV_ACC_RAM(i)      <= conv_std_logic_vector(0,MAX_DWIDTH);
    cmd_DIV_ACC_RAM(i)      <= conv_std_logic_vector(43,6);
    -- Instantiate the ALU unit with the data width set to i
    i_mc8051_alu_DIV_ACC_RAM : mc8051_alu    
      generic map (                 
        DWIDTH => i)                
      port map (