tb_mc8051_alu_sim.vhd

这是用C语言编写的关于8051的VHDL的源代码

          v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
          s_cyo <= v_flags(((DWIDTH-1)/4) downto 0);
          s_ovo <= v_flags(v_flags'HIGH);        
          v_product := j*i;
          wait for PROP_DELAY;
          if v_product > 2**DWIDTH-1 then
            assert (s_cyi((DWIDTH-1)/4) = '0')
              and (s_ovi = '1')
              and (s_product = conv_std_logic_vector(v_product,DWIDTH*2))
              report "ERROR in " & IMAGE(DWIDTH) & "bit multiplication!"
              severity failure;
          else  
            assert (s_cyi((DWIDTH-1)/4) = '0')
              and (s_product = conv_std_logic_vector(v_product,DWIDTH*2))
              and (s_ovi = '0')
              report "ERROR in " & IMAGE(DWIDTH) & "bit multiplication!"
              severity failure;
          end if;
        end loop;  -- f
      end loop;  -- i
    end loop;  -- j  
    assert false
      report "********* " & IMAGE(DWIDTH)
      & "BIT MULTIPLIER SEQUENCE FINISHED AT "
      & IMAGE(now) & " !" & " *********" 
      severity note;
    s_mul_end <= true;
    wait;
  end PROC_MUL_ACC_RAM;
  -----------------------------------------------------------------------------
  
  -----------------------------------------------------------------------------
  --                                                                         --
  --  PROC_AND - Test the logical AND command                                --
  --                                                                         --
  --  Procedure to generate all the input data to test the logical           --
  --  AND command. Furthermore the results are compared with the             --
  --  expected values and the simulation is stopped with an error message    --
  --  if the test failes.                                                    --
  -----------------------------------------------------------------------------
  procedure PROC_AND (
    constant DWIDTH     : in  positive;
    constant PROP_DELAY : in  time;
    signal   s_cyi      : in  std_logic_vector;
    signal   s_ovi      : in  std_logic;
    signal   s_result   : in  std_logic_vector;
    signal   s_cyo      : out std_logic_vector;
    signal   s_ovo      : out std_logic;
    signal   s_operanda : out std_logic_vector;
    signal   s_operandb : out std_logic_vector;
    signal   s_and_end  : out boolean) is

    variable v_result : std_logic_vector(DWIDTH-1 downto 0);
    variable v_flags  : std_logic_vector((DWIDTH-1)/4+1 downto 0);
    variable v_cyo    : std_logic_vector(((DWIDTH-1)/4) downto 0);
    variable v_ovo    : std_logic;

  begin
    s_and_end <= false;
    for j in 0 to 2**DWIDTH-1 loop
      s_operanda <= conv_std_logic_vector(j,DWIDTH);
      for i in 0 to 2**DWIDTH-1 loop
        s_operandb <= conv_std_logic_vector(i,DWIDTH);
        for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
          v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
          v_cyo := v_flags(((DWIDTH-1)/4) downto 0);
          v_ovo := v_flags(v_flags'HIGH);
          s_cyo <= v_cyo;
          s_ovo <= v_ovo;
          v_result := conv_std_logic_vector(j,DWIDTH)
                      and conv_std_logic_vector(i,DWIDTH);
          wait for PROP_DELAY;
          assert (s_cyi = v_cyo)
            and (s_ovi = v_ovo)
            and (s_result = v_result)
            report "ERROR in " & IMAGE(DWIDTH) & "bit logical AND operation!"
            severity failure;
        end loop;  -- f
      end loop;  -- i
    end loop;  -- j  
    assert false
      report "********* " & IMAGE(DWIDTH)
      & "BIT AND SEQUENCE FINISHED AT "
      & IMAGE(now) & " !" & " *********" 
      severity note;
    s_and_end <= true;
    wait;
  end PROC_AND;
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  --                                                                         --
  --  PROC_OR - Test the logical OR command                                  --
  --                                                                         --
  --  Procedure to generate all the input data to test the logical           --
  --  OR command. Furthermore the results are compared with the              --
  --  expected values and the simulation is stopped with an error message    --
  --  if the test failes.                                                    --
  -----------------------------------------------------------------------------
  procedure PROC_OR (
    constant DWIDTH     : in  positive;
    constant PROP_DELAY : in  time;
    signal   s_cyi      : in  std_logic_vector;
    signal   s_ovi      : in  std_logic;
    signal   s_result   : in  std_logic_vector;
    signal   s_cyo      : out std_logic_vector;
    signal   s_ovo      : out std_logic;
    signal   s_operanda : out std_logic_vector;
    signal   s_operandb : out std_logic_vector;
    signal   s_or_end  : out boolean) is

    variable v_result : std_logic_vector(DWIDTH-1 downto 0);
    variable v_flags  : std_logic_vector((DWIDTH-1)/4+1 downto 0);
    variable v_cyo    : std_logic_vector(((DWIDTH-1)/4) downto 0);
    variable v_ovo    : std_logic;

  begin
    s_or_end <= false;
    for j in 0 to 2**DWIDTH-1 loop
      s_operanda <= conv_std_logic_vector(j,DWIDTH);
      for i in 0 to 2**DWIDTH-1 loop
        s_operandb <= conv_std_logic_vector(i,DWIDTH);
        for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
          v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
          v_cyo := v_flags(((DWIDTH-1)/4) downto 0);
          v_ovo := v_flags(v_flags'HIGH);
          s_cyo <= v_cyo;
          s_ovo <= v_ovo;
          v_result := conv_std_logic_vector(j,DWIDTH)
                      or conv_std_logic_vector(i,DWIDTH);
          wait for PROP_DELAY;
          assert (s_cyi = v_cyo)
            and (s_ovi = v_ovo)
            and (s_result = v_result)
            report "ERROR in " & IMAGE(DWIDTH) & "bit logical OR operation!"
            severity failure;
        end loop;  -- f
      end loop;  -- i
    end loop;  -- j  
    assert false
      report "********* " & IMAGE(DWIDTH)
      & "BIT OR SEQUENCE FINISHED AT "
      & IMAGE(now) & " !" & " *********" 
      severity note;
    s_or_end <= true;
    wait;
  end PROC_OR;
  -----------------------------------------------------------------------------
  
  -----------------------------------------------------------------------------
  --                                                                         --
  --  PROC_XOR - Test the logical XOR command                                --
  --                                                                         --
  --  Procedure to generate all the input data to test the logical           --
  --  XOR command. Furthermore the results are compared with the             --
  --  expected values and the simulation is stopped with an error message    --
  --  if the test failes.                                                    --
  -----------------------------------------------------------------------------
  procedure PROC_XOR (
    constant DWIDTH     : in  positive;
    constant PROP_DELAY : in  time;
    signal   s_cyi      : in  std_logic_vector;
    signal   s_ovi      : in  std_logic;
    signal   s_result   : in  std_logic_vector;
    signal   s_cyo      : out std_logic_vector;
    signal   s_ovo      : out std_logic;
    signal   s_operanda : out std_logic_vector;
    signal   s_operandb : out std_logic_vector;
    signal   s_xor_end  : out boolean) is

    variable v_result : std_logic_vector(DWIDTH-1 downto 0);
    variable v_flags  : std_logic_vector((DWIDTH-1)/4+1 downto 0);
    variable v_cyo    : std_logic_vector(((DWIDTH-1)/4) downto 0);
    variable v_ovo    : std_logic;

  begin
    s_xor_end <= false;
    for j in 0 to 2**DWIDTH-1 loop
      s_operanda <= conv_std_logic_vector(j,DWIDTH);
      for i in 0 to 2**DWIDTH-1 loop
        s_operandb <= conv_std_logic_vector(i,DWIDTH);
        for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
          v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
          v_cyo := v_flags(((DWIDTH-1)/4) downto 0);
          v_ovo := v_flags(v_flags'HIGH);
          s_cyo <= v_cyo;
          s_ovo <= v_ovo;
          v_result := conv_std_logic_vector(j,DWIDTH)
                      xor conv_std_logic_vector(i,DWIDTH);
          wait for PROP_DELAY;
          assert (s_cyi = v_cyo)
            and (s_ovi = v_ovo)
            and (s_result = v_result)
            report "ERROR in " & IMAGE(DWIDTH) & "bit logical XOR operation!"
            severity failure;
        end loop;  -- f
      end loop;  -- i
    end loop;  -- j  
    assert false
      report "********* " & IMAGE(DWIDTH)
      & "BIT XOR SEQUENCE FINISHED AT "
      & IMAGE(now) & " !" & " *********" 
      severity note;
    s_xor_end <= true;
    wait;
  end PROC_XOR;
  -----------------------------------------------------------------------------
  
  -----------------------------------------------------------------------------
  --                                                                         --
  --  PROC_ADD - Test the logical ADD command                                --
  --                                                                         --
  --  Procedure to generate all the input data to test the logical           --
  --  ADD command. Furthermore the results are compared with the             --
  --  expected values and the simulation is stopped with an error message    --
  --  if the test failes.                                                    --
  -----------------------------------------------------------------------------
  procedure PROC_ADD (
    constant DWIDTH     : in  positive;
    constant PROP_DELAY : in  time;
    constant ADD_CARRY  : in  boolean;
    signal   s_cyi      : in  std_logic_vector;
    signal   s_ovi      : in  std_logic;
    signal   s_result   : in  std_logic_vector;
    signal   s_cyo      : out std_logic_vector;
    signal   s_ovo      : out std_logic;
    signal   s_operanda : out std_logic_vector;
    signal   s_operandb : out std_logic_vector;
    signal   s_add_end  : out boolean) is

    variable v_result : std_logic_vector(DWIDTH-1 downto 0);
    variable v_flags  : std_logic_vector((DWIDTH-1)/4+1 downto 0);
    variable v_cyo    : std_logic_vector(((DWIDTH-1)/4) downto 0);
    variable v_ovo    : std_logic;
    variable v_carry  : integer;

  begin
    s_add_end <= false;
    for j in 0 to 2**DWIDTH-1 loop
      s_operanda <= conv_std_logic_vector(j,DWIDTH);
      for i in 0 to 2**DWIDTH-1 loop
        s_operandb <= conv_std_logic_vector(i,DWIDTH);
        for f in 0 to 2**(((DWIDTH-1)/4)+2)-1 loop
          v_flags := conv_std_logic_vector(f,((DWIDTH-1)/4)+2);
          s_cyo <= v_flags(((DWIDTH-1)/4) downto 0);
          s_ovo <= v_flags(v_flags'HIGH);
          v_carry := conv_integer(v_flags((DWIDTH-1)/4));
          if ADD_CARRY = true then
            for h in 0 to (DWIDTH-1)/4 loop
              if DWIDTH > (h+1)*4 then
                if (j mod 2**((h+1)*4) + i mod 2**((h+1)*4) + v_carry)
                  > 2**((h+1)*4)-1 then  
                  v_cyo(h) := '1';                          
                else                                        
                  v_cyo(h) := '0';                          
                end if;
              else
                if (j mod 2**(DWIDTH) + i mod 2**(DWIDTH) + v_carry
                  > 2**(DWIDTH)-1) then  
                  v_cyo(h) := '1';                          
                else                                        
                  v_cyo(h) := '0';                          
                end if;
              end if;
            end loop;  -- h
 --           if DWIDTH = 1 then
 --             v_ovo := '0';
 --           else
              if (j+i > 2**DWIDTH-1
                  and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1) + v_carry)
                  <= 2**(DWIDTH-1)-1) or
                (j+i < 2**DWIDTH-1
                 and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1) + v_carry)
                 > 2**(DWIDTH-1)-1) then
                v_ovo := '1';                             
              else                                          
                v_ovo := '0';                               
              end if;                                       
 --           end if;
            v_result := conv_std_logic_vector(j + i + v_carry,DWIDTH);
            wait for PROP_DELAY;
            assert (s_cyi = v_cyo)
              and (s_ovi = v_ovo)
              and (s_result = v_result)
              report "ERROR in " & IMAGE(DWIDTH) & "bit ADDC operation!"
              severity failure;
          else
            for h in 0 to (DWIDTH-1)/4 loop
              if DWIDTH > (h+1)*4 then
                if (j mod 2**((h+1)*4) + i mod 2**((h+1)*4))
                  > 2**((h+1)*4)-1 then  
                  v_cyo(h) := '1';                          
                else                                        
                  v_cyo(h) := '0';                          
                end if;
              else
                if (j mod 2**(DWIDTH) + i mod 2**(DWIDTH)
                  > 2**(DWIDTH)-1) then  
                  v_cyo(h) := '1';                          
                else                                        
                  v_cyo(h) := '0';                          
                end if;
              end if;
            end loop;  -- h
 --           if DWIDTH = 1 then
 --             v_ovo := '0';
 --           else
              if (j+i > 2**DWIDTH-1
                  and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1))
                  <= 2**(DWIDTH-1)-1) or
                (j+i <= 2**DWIDTH-1
                 and (j mod 2**(DWIDTH-1) + i mod 2**(DWIDTH-1))
                 > 2**(DWIDTH-1)-1) then
                v_ovo := '1';                               
              else                                          
                v_ovo := '0';                               
              end if;                                       
 --           end if;
            v_result := conv_std_logic_vector(j+i,DWIDTH);
            wait for PROP_DELAY;
            assert (s_cyi = v_cyo)