📄 tb_mc8051_core_sim.vhd
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--------------------------------------------------------------------------------- ---- X X XXXXXX XXXXXX XXXXXX XXXXXX X ---- XX XX X X X X X X X XX ---- X X X X X X X X X X X X ---- X X X X X X X X X X X X ---- X X X X XXXXXX X X XXXXXX X ---- X X X X X X X X X ---- X X X X X X X X X ---- X X X X X X X X X X ---- X X XXXXXX XXXXXX XXXXXX XXXXXX X ---- ---- ---- O R E G A N O S Y S T E M S ---- ---- Design & Consulting ---- ----------------------------------------------------------------------------------- ---- Web: http://www.oregano.at/ ---- ---- Contact: mc8051@oregano.at ---- ----------------------------------------------------------------------------------- ---- MC8051 - VHDL 8051 Microcontroller IP Core ---- Copyright (C) 2001 OREGANO SYSTEMS ---- ---- This library is free software; you can redistribute it and/or ---- modify it under the terms of the GNU Lesser General Public ---- License as published by the Free Software Foundation; either ---- version 2.1 of the License, or (at your option) any later version. ---- ---- This library is distributed in the hope that it will be useful, ---- but WITHOUT ANY WARRANTY; without even the implied warranty of ---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ---- Lesser General Public License for more details. ---- ---- Full details of the license can be found in the file LGPL.TXT. ---- ---- You should have received a copy of the GNU Lesser General Public ---- License along with this library; if not, write to the Free Software ---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ---- --------------------------------------------------------------------------------------- Author: Helmut Mayrhofer---- Filename: tb_mc8051_core_sim.vhd---- Date of Creation: Mon Aug 9 12:14:48 1999---- Version: $Revision: 1.2 $---- Date of Latest Version: $Date: 2002/01/07 12:16:57 $------ Description: The mc8051 core level testbench.---------------------------------------------------------------------------------------architecture sim of tb_mc8051_core is signal s_p0_i : std_logic_vector(7 downto 0); signal s_p1_i : std_logic_vector(7 downto 0); signal s_p2_i : std_logic_vector(7 downto 0); signal s_p3_i : std_logic_vector(7 downto 0); signal s_p0_o : std_logic_vector(7 downto 0); signal s_p1_o : std_logic_vector(7 downto 0); signal s_p2_o : std_logic_vector(7 downto 0); signal s_p3_o : std_logic_vector(7 downto 0); signal clk : std_logic; signal reset : std_logic; signal s_int0 : std_logic; signal s_int1 : std_logic; signal s_t0_n0 : std_logic; signal s_t1_n0 : std_logic; signal s_t0_n1 : std_logic; signal s_t1_n1 : std_logic; signal s_t0_n2 : std_logic; signal s_t1_n2 : std_logic; signal s_t0_n3 : std_logic; signal s_t1_n3 : std_logic; signal s_t0_n4 : std_logic; signal s_t1_n4 : std_logic; signal s_rxd_n0 : std_logic; signal s_rxd_n1 : std_logic; signal s_rxd_n2 : std_logic; signal s_rxd_n3 : std_logic; signal s_rxd_n4 : std_logic; signal s_rxd_n0_o : std_logic; signal s_rxd_n1_o : std_logic; signal s_rxd_n2_o : std_logic; signal s_rxd_n3_o : std_logic; signal s_rxd_n4_o : std_logic; signal s_txd_n0 : std_logic; signal s_txd_n1 : std_logic; signal s_txd_n2 : std_logic; signal s_txd_n3 : std_logic; signal s_txd_n4 : std_logic; begin i_mc8051_core : mc8051_core port map (reset => reset, int0_i => s_int0, int1_i => s_int1, t0_n0_i => s_t0_n0, t1_n0_i => s_t1_n0, t0_n1_i => s_t0_n1, t1_n1_i => s_t1_n1, t0_n2_i => s_t0_n2, t1_n2_i => s_t1_n2, t0_n3_i => s_t0_n3, t1_n3_i => s_t1_n3, t0_n4_i => s_t0_n4, t1_n4_i => s_t1_n4, rxd_n0_i => s_rxd_n0, rxd_n1_i => s_rxd_n1, rxd_n2_i => s_rxd_n2, rxd_n3_i => s_rxd_n3, rxd_n4_i => s_rxd_n4, rxd_n0_o => s_rxd_n0_o, rxd_n1_o => s_rxd_n1_o, rxd_n2_o => s_rxd_n2_o, rxd_n3_o => s_rxd_n3_o, rxd_n4_o => s_rxd_n4_o, txd_n0_o => s_txd_n0, txd_n1_o => s_txd_n1, txd_n2_o => s_txd_n2, txd_n3_o => s_txd_n3, txd_n4_o => s_txd_n4, clk => clk, p0_i => s_p0_i, p1_i => s_p1_i, p2_i => s_p2_i, p3_i => s_p3_i, p0_o => s_p0_o, p1_o => s_p1_o, p2_o => s_p2_o, p3_o => s_p3_o); p_run : process begin--------------------------------------------------------------------------------- set start values and perform reset------------------------------------------------------------------------------- s_p0_i <= "00000000"; s_p1_i <= "00000000"; s_p2_i <= "00000000"; s_p3_i <= "00000000"; s_int0 <= '0'; s_int1 <= '0'; s_t0_n0 <= '0'; s_t1_n0 <= '0'; s_t0_n1 <= '0'; s_t1_n1 <= '0'; s_t0_n2 <= '0'; s_t1_n2 <= '0'; s_t0_n3 <= '0'; s_t1_n3 <= '0'; s_t0_n4 <= '0'; s_t1_n4 <= '0'; s_rxd_n0 <= '0'; s_rxd_n1 <= '0'; s_rxd_n2 <= '0'; s_rxd_n3 <= '0'; s_rxd_n4 <= '0'; reset <= '1'; wait for one_period + one_period/2 + 5 ns; reset <= '0'; wait for one_period * 50; wait for one_period / 2; assert false report "END OF SIMULATION" severity failure; end process p_run;-- system clock definition p_clock : process variable v_loop1 : integer; begin clk <= '0'; wait for one_period/2; while true loop clk <= not clk; wait for one_period/2; end loop; end process p_clock;end sim;⌨️ 快捷键说明
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