meclibrary.vhd

ERC32 经典的sparc v7 cpu

----------------------------------------------------------------------------

    -- MReset high for 2 Clk period, It is used by the UARTs as 
    -- an asynchronous reset
    -- The UARTs are working on the rising edge so the 
    -- aynchronous reset is generated on ck+
    MasterReset: process(Reset_Int_N, Clk_Int)
    type states is (S0, S1);
    variable state :states;
    begin
      if Reset_Int_N = '0' then
        MReset_A <= '1';
        MReset_B <= '1';
        state    := S1;
          
      elsif Clk_Int'event and Clk_Int='1' then
        case state is
           when S0 => if (UARTStatusReg_N = '0') and (Wr_Int_N = '0') then
                         MReset_A <= D7;
                         MReset_B <= D23;
                         state := S1;
                       else
                         MReset_A <= '0';
                         MReset_B <= '0';
                         state := S0;
                       end if;
                       
           when S1 => state:=S0;
         end case;
      end if;
    end process;


----------------------------------------------------------------------------
    DataReadyReset: process(Reset_Int_N, Clk_Int)
    begin
                
     if Reset_Int_N = '0' then
         D_ReadyRes_A_N <= '1';
         D_ReadyRes_B_N <= '1';
          
     elsif Clk_Int'event and Clk_Int = '1' then
     
       if Rd_Int_In = '1' and DoNotRdUART = '0' and 
          GUARTAReg_N = '0' and D_Ready_A = '1' then
         D_ReadyRes_A_N <= '0';
         D_ReadyRes_B_N <= '1';
       elsif Rd_Int_In = '1' and DoNotRdUART = '0' and 
             GUARTBReg_N = '0' and D_Ready_B = '1' then
         D_ReadyRes_A_N <= '1';
         D_ReadyRes_B_N <= '0';
       else
         D_ReadyRes_A_N <= '1';
         D_ReadyRes_B_N <= '1';
       end if;
            
     end if;
        
    end process;
    

----------------------------------------------------------------------------
    WriteStrobes: process(Reset_Int_N, Clk_Int)
    begin
     if Reset_Int_N = '0' then
        Wr_Data_A_N <= '1';
        Wr_Data_B_N <= '1';
        Wr_Control  <= '0';

     elsif Clk_Int'event and Clk_Int='0' then
        Wr_Data_A_N <= Wr_Int_N or UARTAReg_N;
        Wr_Data_B_N <= Wr_Int_N or UARTBReg_N;
        Wr_Control  <= not (Wr_Int_N or MECControlReg_N);
     end if;
    end process;

----------------------------------------------------------------------------
    -- Sample signals for UART A RX/TX Register
    UART_A_Reg1(7 downto 0)      <= D_UART_A_Out;
  --  UART_A_Reg1(8)               <= D_Ready_A and not(Frame_Err_A or Par_Err_A or O_Err_A);
  --  UART_A_Reg1(9)               <= TrSeRegEm_A;
  --  UART_A_Reg1(10)              <= TrHoRegEm_A;
    UART_A_Par1                  <= ParityGen(UART_A_Reg1);
            
    -- Sample signals for UART B RX/TX Register
    UART_B_Reg1(7 downto 0)      <= D_UART_B_Out;
  --  UART_B_Reg1(8)               <= D_Ready_B and not(Frame_Err_B or Par_Err_B or O_Err_B);
  --  UART_B_Reg1(9)               <= TrSeRegEm_B;
  --  UART_B_Reg1(10)              <= TrHoRegEm_B;
    UART_B_Par1                  <= ParityGen(UART_B_Reg1);
           
    -- Sample signals for UART Status Register
    UART_Status_Reg1(0)          <= D_Ready_A and not(Frame_Err_A or Par_Err_A or O_Err_A);
    UART_Status_Reg1(1)          <= TrSeRegEm_A;
    UART_Status_Reg1(2)          <= TrHoRegEm_A;
    UART_Status_Reg1(3)          <= '0';
    UART_Status_Reg1(4)          <= Frame_Err_A;
    UART_Status_Reg1(5)          <= Par_Err_A;
    UART_Status_Reg1(6)          <= O_Err_A;
    UART_Status_Reg1(15 downto 7)<= "000000000";
    UART_Status_Reg1(16)         <= D_Ready_B and not(Frame_Err_B or Par_Err_B or O_Err_B);
    UART_Status_Reg1(17)         <= TrSeRegEm_B;
    UART_Status_Reg1(18)         <= TrHoRegEm_B;
    UART_Status_Reg1(19)         <= '0';
    UART_Status_Reg1(20)         <= Frame_Err_B;
    UART_Status_Reg1(21)         <= Par_Err_B;
    UART_Status_Reg1(22)         <= O_Err_B;
    UART_Status_Reg1(23)         <= '0';
    UART_Status_Par1             <= ParityGen(UART_Status_Reg1);

    DataSampleProc1: process(Clk_Int)
    begin
     if Clk_Int'event and Clk_Int = '1' then
     
       if Rd_Int_In = '1' and GUARTAReg_N = '0' then
          UART_A_Reg      <= UART_A_Reg;
          UART_A_Par      <= UART_A_Par;
       else
          UART_A_Reg      <= UART_A_Reg1;
          UART_A_Par      <= UART_A_Par1;
       end if;
            
     end if;
        
    end process;
    
    DataSampleProc2: process(Clk_Int)
    begin
     if Clk_Int'event and Clk_Int = '1' then
     
       if Rd_Int_In = '1' and GUARTBReg_N = '0' then
          UART_B_Reg      <= UART_B_Reg;
          UART_B_Par      <= UART_B_Par;
       else
          UART_B_Reg      <= UART_B_Reg1;
          UART_B_Par      <= UART_B_Par1;
       end if;
            
     end if;
        
    end process;
    
    DataSampleProc3: process(Clk_Int)
    begin
     if Clk_Int'event and Clk_Int = '1' then
     
       if Rd_Int_In = '1' and GUARTStatusReg_N = '0' then
          UART_Status_Reg(6 downto 0)    <= UART_Status_Reg(6 downto 0);
          UART_Status_Reg(22 downto 16)  <= UART_Status_Reg(22 downto 16);
          UART_Status_Par                <= UART_Status_Par;
       else
          UART_Status_Reg(6 downto 0)    <= UART_Status_Reg1(6 downto 0);
          UART_Status_Reg(22 downto 16)  <= UART_Status_Reg1(22 downto 16);
          UART_Status_Par                <= UART_Status_Par1;
       end if;
            
     end if;
        
    end process;
    
        
 process(UART_A_Reg,UART_A_Par,UART_B_Reg,UART_B_Par,
         UART_Status_Reg,UART_Status_Par)    
 begin
    D_UARTA_Out(7 downto 0)   <= UART_A_Reg;
    D_UARTA_Out(31 downto 8)  <= "000000000000000000000000";
    DPar_UARTA_Out            <= UART_A_Par;

    D_UARTB_Out(7 downto 0)   <= UART_B_Reg;
    D_UARTB_Out(31 downto 8)  <= "000000000000000000000000";
    DPar_UARTB_Out            <= UART_B_Par;
            
    D_UARTS_Out(6 downto 0)   <= UART_Status_Reg(6 downto 0);
    D_UARTS_Out(15 downto 7)  <= "000000000";
    D_UARTS_Out(22 downto 16) <= UART_Status_Reg(22 downto 16);
    D_UARTS_Out(31 downto 23) <= "000000000";
    DPar_UARTS_Out            <= UART_Status_Par;
            
 end process;


end Mini_Spec ;



---------------------------------------------------------------------------
--                Copyright MATRA MARCONI SPACE FRANCE                   --
---------------------------------------------------------------------------
--  The ownership and copyright of this document belong to               --
--  MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied,     --
--  altered or used without the written                                  --
--  permission of MATRA MARCONI SPACE FRANCE.                            --
---------------------------------------------------------------------------
-- Title:                      UART control
-- File name:                  \mec\source\uarts.vhd
-- VHDL unit:                   UARTs 
-- Reference:                  (RDx)
-- Analysis Dependencies:      (N/A)
-- Limitations:                (N/A)
-- Fidelity:                   (N/A)
-- Discrepancies:              (N/A)
-- Usage:                      (N/A)
-- I/O:                        (N/A)
-- Operations:                 (N/A)
-- Assertions:                 (N/A)
-- Development Platform:       (N/A)
-- Analyzer:                   (No Dependencies)
-- Synthesis:                  (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included)                            --
---------------------------------------------------------------------------
-- Version No:    Author:            Modification Date:    Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A    Remi CISSOU           1996-04-22           New issue
--
---------------------------------------------------------------------------
--

library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;

library IEEE;
use IEEE.Std_Logic_1164.all;



entity UARTs is
port (
          Clk_Int          : in Std_Logic;
          UART_Clk_En      : in Std_Logic;
          Reset_Int_N      : in Std_Logic;
                    
          DoNotRdUART      : in Std_Logic;
           
          GUARTAReg_N      : in Std_Logic;
          GUARTBReg_N      : in Std_Logic;
          GUARTStatusReg_N : in Std_Logic;
                    
          UARTAReg_N       : in Std_Logic;
          UARTBReg_N       : in Std_Logic;
          UARTStatusReg_N  : in Std_Logic;
          MECControlReg_N  : in Std_Logic;
          Wr_Int_N         : in Std_Logic;
          Rd_Int_In        : in Std_Logic;
          D_Int_In         : in Std_Logic_Vector(31 downto 0);
          RxA_In           : in Std_Logic;
          RxB_In           : in Std_Logic;

          TxA_Out          : out Std_Logic;
          TxB_Out          : out Std_Logic;
          Intr_UARTA_Data  : out Std_Logic;
          Intr_UARTB_Data  : out Std_Logic;
          UARTs_Quiet      : out Std_Logic;
          Intr_UART_Err    : out Std_Logic;
          D_UARTA_Out      : out Std_Logic_Vector(31 downto 0);
          DPar_UARTA_Out   : out Std_Logic;
          D_UARTB_Out      : out Std_Logic_Vector(31 downto 0);
          DPar_UARTB_Out   : out Std_Logic;
          D_UARTS_Out      : out Std_Logic_Vector(31 downto 0);
          DPar_UARTS_Out   : out Std_Logic
     );
end UARTs;

architecture Mini_spec of UARTs is

component UART 
    port (
          MCK           : in std_logic;   -- MEC clock
          TBR1          : in Std_Logic;   -- D_UART_In(0)
          TBR2          : in Std_Logic;   -- D_UART_In(1)
          TBR3          : in Std_Logic;   -- D_UART_In(2)
          TBR4          : in Std_Logic;   -- D_UART_In(3)
          TBR5          : in Std_Logic;   -- D_UART_In(4)
          TBR6          : in Std_Logic;   -- D_UART_In(5)
          TBR7          : in Std_Logic;   -- D_UART_In(6)
          TBR8          : in Std_Logic;   -- D_UART_In(7)

          TBRL_N          : in Std_Logic;   -- Wr_Data_N
          CRL           : in Std_Logic;   -- Wr_Control
          SBS           : in Std_Logic;   -- SBSel
          
          PI            : in Std_Logic;   -- ParInh
          EPE           : in Std_Logic;   -- EvenOdd_N
          
          DRR           : in Std_Logic;   -- D_ReadyRes_N
          
          TRC           : in Std_Logic;   -- UART_Clk_En_T
          
          RRC           : in Std_Logic;   -- UART_Clk_En_R
          
          RRI           : in Std_Logic;   -- Rx_In
          
          MR            : in Std_Logic;   -- MReset
          
          RBR1          : out Std_Logic;  -- D_UART_Out(0)
          RBR2          : out Std_Logic;  -- D_UART_Out(1)
          RBR3          : out Std_Logic;  -- D_UART_Out(2)
          RBR4          : out Std_Logic;  -- D_UART_Out(3)
          RBR5          : out Std_Logic;  -- D_UART_Out(4)
          RBR6          : out Std_Logic;  -- D_UART_Out(5)
          RBR7          : out Std_Logic;  -- D_UART_Out(6)
          RBR8          : out Std_Logic;  -- D_UART_Out(7)
          
          DR            : out Std_Logic;  -- D_Ready
          
          TBRE          : out Std_Logic;  -- TrHoRegEm
          TRE           : out Std_Logic;  -- TrSeRegEm
          
          FE            : out Std_Logic;  -- Frame_Err
          PE            : out Std_Logic;  -- Par_Err
          OE            : out Std_Logic;  -- O_Err
          
          TRO           : out Std_Logic  -- Tx_Out
         );
end component;

component UARTControl 
port (
          Clk_Int         : in Std_Logic;
          Reset_Int_N     : in Std_Logic;
          DoNotRdUART     : in Std_Logic;
           
          GUARTAReg_N      : in Std_Logic;
          GUARTBReg_N      : in Std_Logic;
          GUARTStatusReg_N : in Std_Logic;
                    
          UARTAReg_N      : in Std_Logic;
          UARTBReg_N      : in Std_Logic;
          UARTStatusReg_N : in Std_Logic;
          MECControlReg_N : in Std_Logic;
          Wr_Int_N        : in Std_Logic;
          Rd_Int_In       : in Std_Logic;
          D_Int_In        : in Std_Logic_Vector(31 downto 0);
          
          Intr_UARTA_Data  : out Std_Logic;
          Intr_UARTB_Data  : out Std_Logic;
          UARTs_Quiet     : out Std_Logic;
          Intr_UART_Err   : out Std_Logic;
          
          D_UARTA_Out     : out Std_Logic_Vector(31 downto 0);
          DPar_UARTA_Out  : out Std_Logic;
          D_UARTB_Out     : out Std_Logic_Vector(31 downto 0);
          DPar_UARTB_Out  : out Std_Logic;
          D_UARTS_Out     : out Std_Logic_Vector(31 downto 0);
          DPar_UARTS_Out  : out Std_Logic;

          D_Ready_A     : in Std_Logic;
          D_Ready_B     : in Std_Logic;
          O_Err_A       : in Std_Logic;
          O_Err_B       : in Std_Logic;
          Frame_Err_A   : in Std_Logic;
          Frame_Err_B   : in Std_Logic;
          Par_Err_A     : in Std_Logic;
          Par_Err_B     : in Std_Logic;
          TrHoRegEm_A   : in Std_Logic;
          TrHoRegEm_B   : in Std_Logic;
          TrSeRegEm_A   : in Std_Logic;
          TrSeRegEm_B   : in Std_Logic;
          D_UART_A_Out  : in Std_Logic_Vector(7 downto 0);
          D_UART_B_Out  : in Std_Logic_Vector(7 downto 0);

          MReset_A      : out Std_Logic;
          MReset_B      : out S