meclibrary.vhd

来自「ERC32 经典的sparc v7 cpu」· VHDL 代码 · 共 1,832 行 · 第 1/5 页

       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  parity bit if any
    when ZD10 => 
     if SampleRec = '1' then
       Next_SRec <= ZD11;       -- 1 st stop bit
       ParBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  first stop bit
    when ZD11 => 
     if SampleRec = '1' then
       if SBSReg = '1' then
         Next_SRec <= ZD12;    -- second stop bit
       else
         Next_SRec <= ZD13;    -- only 1 stop bit
       end if;
       FirstStopBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  the second stop bit (if 2 stop bits)
    when ZD12 => 
     if SampleRec = '1' then
       Next_SRec <= ZD13;
     end if;
     EnCountClkRec <= '1';
    
  -- end
     when ZD13 =>
  -- return to ZD0 only if a level 1 was detected
       if RRI_R = '1' then
         Next_Srec <= ZD0;  -- TBC
       end if;
     
     when others =>
       Next_Srec <= ZD0;
    end case;

end process;

----------------------------------------------------------------------------
-- Receive Shift Register 
-- The register is shifted at each sample
--
RecRegProc : process(MCK, MR)
begin
  if (MR = '1') then
    ReceiveReg   <= "00000000";
  
  elsif (MCK'event and MCK = '1') then
    if DataBitSampled = '1' then
      ReceiveReg(0) <= ReceiveReg(1);
      ReceiveReg(1) <= ReceiveReg(2);
      ReceiveReg(2) <= ReceiveReg(3);
      ReceiveReg(3) <= ReceiveReg(4);
      ReceiveReg(4) <= ReceiveReg(5);
      ReceiveReg(5) <= ReceiveReg(6);
      ReceiveReg(6) <= ReceiveReg(7);
      ReceiveReg(7) <= RRI_R;
    end if;
  end if;
end process;

----------------------------------------------------------------------------
-- Receive Buffer Register 
-- This register is loaded by the fsm during the first stop bit
--
ReceiveProc: process(MCK, MR)
begin
  if (MR = '1') then
    RecBufReg   <= "00000000";  
  elsif (MCK'event and MCK = '1') then
    if FirstStopBitSampled = '1' then
      RecBufReg <= ReceiveReg;
    end if;
  end if;
end process;

----------------------------------------------------------------------------
-- This process manages the Parity for the receive part
-- when the receiving process starts  the ParecReg is set to 1 or 0 depending
--  on the parity to compute
-- Then for each data bit received parity is computed and memorized
-- When the parity bit is received it is compared to the ParecReg regiter (parity ODD/EVEN)
-- if the result is false it is set to 1.
-- The value of this register is loaded in PEReg at the same time as RBR reg
-- 
ParityCompute: process(MCK, MR)
begin
  if (MR = '1') then
    ParecReg <= '0';
  
  elsif (MCK'event and MCK = '1') then
    if StartBitSampled = '1' then     -- initialise parity computation
    	ParecReg <= not EPEReg;    -- 0 for Even Parity 1 for Odd parity
    	
    elsif DataBitSampled = '1' then  -- compute parity
    	ParecReg <= ParecReg xor RRI_R;
    	
    elsif ParBitSampled = '1' then  -- test parity
        if Parecreg = RRI_R then
          ParecReg <= '0';       -- Parity good 
        else
          ParecReg <= '1';       -- Parity wrong
        end if;
    end if;
  end if; 

end process;

----------------------------------------------------------------------------
-- Computation of the Frame Error Error, Parity Error
-- Frame Errot is Active if the first stop bit is not at 1
--
FEprocess: process(MCK, MR)
begin
  if (MR = '1') then
    FEReg <= '0';
    PEReg <= '0';
  elsif (MCK'event and MCK = '1') then
  
-- NOTE : TO BE CORRECTED DR and FE shall be generated later

    if FirstStopBitSampled = '1' then
    
      if RRI_R = '0' then
     --rc   FEReg <= '1';    -- error first stop bit is zero
        FEReg <= '1' or FEReg;    -- error first stop bit is zero
      else
        FEReg <= '0';    -- no error    
      end if;
      
      if PIReg = '1' then
        PEReg <= '0';     -- no parity => no parity error
      else
     --rc   PEReg <= Parecreg;
        PEReg <= Parecreg or PEReg; -- hold the error until MR activation
      end if;
      
    end if;
  end if;
end process;

----------------------------------------------------------------------------
-- Data ready and Overrun Error management
-- Data Ready is cleared by the DRR signal and set when data is transferred (1st stop bit)
-- Overrun error is set to 1 if DRreg is active when First Stop Bit

OEProcess: process(MCK, MR)
begin
  if (MR = '1') then
    DRReg <= '0';
    OEReg <= '0';
  elsif (MCK'event and MCK = '1') then
    if DRR = '0' then
      DRReg <= '0';                        -- DR clear on DRR high
    elsif FirstStopBitSampled = '1' then
      DRReg <= '1';
    end if;
    
-- NOTE : TO BE CORRECTED DR and FE shall be generated later

    if FirstStopBitSampled = '1' then
      if DRReg = '1' then
        OEReg <= '1';                      -- OE error
      else
        OEReg <= '0';
      end if;
    end if;
  end if;
end process;

end VHDL_RTL;
---------------------------------------------------------------------------
--                Copyright MATRA MARCONI SPACE FRANCE                   --
---------------------------------------------------------------------------
--  The ownership and copyright of this document belong to               --
--  MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied,     --
--  altered or used without the written                                  --
--  permission of MATRA MARCONI SPACE FRANCE.                            --
---------------------------------------------------------------------------
-- Title:                      UART control
-- File name:                  \mec\source\uartctl.vhd
-- VHDL unit:                  UARTControl
-- Purpose and functionality:  
-- Reference:                  (RDx)
-- Analysis Dependencies:      (N/A)
-- Limitations:                (N/A)
-- Fidelity:                   (N/A)
-- Discrepancies:              (N/A)
-- Usage:                      (N/A)
-- I/O:                        (N/A)
-- Operations:                 (N/A)
-- Assertions:                 (N/A)
-- Development Platform:       (N/A)
-- Analyzer:                   (No Dependencies)
-- Synthesis:                  (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included)                            --
---------------------------------------------------------------------------
-- Version No:    Author:            Modification Date:    Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A    Remi CISSOU           1996-04-22           New issue
--
---------------------------------------------------------------------------
--


library MECLibrary;
use MECLibrary.all;
use MECLibrary.MECPackage.all;

library IEEE;
use IEEE.Std_Logic_1164.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity UARTControl is
    port (
          Clk_Int         : in Std_Logic;
          Reset_Int_N     : in Std_Logic;
          DoNotRdUART     : in Std_Logic;
          
          GUARTAReg_N      : in Std_Logic;
          GUARTBReg_N      : in Std_Logic;
          GUARTStatusReg_N : in Std_Logic;
          
          UARTAReg_N      : in Std_Logic;
          UARTBReg_N      : in Std_Logic;
          UARTStatusReg_N : in Std_Logic;
          MECControlReg_N : in Std_Logic;
          Wr_Int_N        : in Std_Logic;
          Rd_Int_In       : in Std_Logic;
          D_Int_In        : in Std_Logic_Vector(31 downto 0);
                    
          Intr_UARTA_Data  : out Std_Logic;
          Intr_UARTB_Data  : out Std_Logic;
          UARTs_Quiet     : out Std_Logic;
          Intr_UART_Err   : out Std_Logic;
          
          D_UARTA_Out     : out Std_Logic_Vector(31 downto 0);
          DPar_UARTA_Out  : out Std_Logic;
          D_UARTB_Out     : out Std_Logic_Vector(31 downto 0);
          DPar_UARTB_Out  : out Std_Logic;
          D_UARTS_Out     : out Std_Logic_Vector(31 downto 0);
          DPar_UARTS_Out  : out Std_Logic;
          
          D_Ready_A       : in Std_Logic;
          D_Ready_B       : in Std_Logic;
          O_Err_A         : in Std_Logic;
          O_Err_B         : in Std_Logic;
          Frame_Err_A     : in Std_Logic;
          Frame_Err_B     : in Std_Logic;
          Par_Err_A       : in Std_Logic;
          Par_Err_B       : in Std_Logic;
          TrHoRegEm_A     : in Std_Logic;
          TrHoRegEm_B     : in Std_Logic;
          TrSeRegEm_A     : in Std_Logic;
          TrSeRegEm_B     : in Std_Logic;
          D_UART_A_Out    : in Std_Logic_Vector(7 downto 0);
          D_UART_B_Out    : in Std_Logic_Vector(7 downto 0);

          MReset_A        : out Std_Logic;
          MReset_B        : out Std_Logic;
          D_ReadyRes_A_N  : out Std_Logic;
          D_ReadyRes_B_N  : out Std_Logic;
          Wr_Data_A_N     : out Std_Logic;
          Wr_Data_B_N     : out Std_Logic;
          Wr_Control      : out Std_Logic;
          SBSel           : out Std_Logic;
          EvenOdd_N       : out Std_Logic;
          ParInh          : out Std_Logic;
          D_UART_In       : out Std_Logic_Vector(7 downto 0)
         );
end UARTControl;

architecture Mini_Spec of UARTControl is

    signal UART_A_Reg1         : Std_Logic_Vector(7 downto 0);
    signal UART_A_Par1         : Std_Logic;
    signal UART_B_Reg1         : Std_Logic_Vector(7 downto 0);
    signal UART_B_Par1         : Std_Logic;
    signal UART_Status_Reg1    : Std_Logic_Vector(23 downto 0);
    signal UART_Status_Par1    : Std_Logic;
    
    signal UART_A_Reg          : Std_Logic_Vector(7 downto 0);
    signal UART_A_Par          : Std_Logic;
    signal UART_B_Reg          : Std_Logic_Vector(7 downto 0);
    signal UART_B_Par          : Std_Logic;
    signal UART_Status_Reg     : Std_Logic_Vector(23 downto 0);
    signal UART_Status_Par     : Std_Logic;
    
    signal TrSeRegEm_A_rck     : Std_Logic;
    signal TrSeRegEm_B_rck     : Std_Logic;
    signal TrSeRegEm_A_redge   : Std_Logic;
    signal TrSeRegEm_B_redge   : Std_Logic;
    
    signal D_Ready_A_rck       : Std_Logic;
    signal D_Ready_B_rck       : Std_Logic;
    signal D_Ready_A_redge     : Std_Logic;
    signal D_Ready_B_redge     : Std_Logic;
    
    signal Intr_UART_Err_rck   : Std_Logic;
        
    signal D7                  : Std_Logic;
    signal D23                 : Std_Logic;
        
begin

----------------------------------------------------------------------------
    Data_Hold: process
    begin
		wait until Clk_Int'event and Clk_Int = '0';
        D7        <=     D_Int_In(7);    
        D23       <=     D_Int_In(23);    
        D_UART_In <=     D_Int_In(7 downto 0);    
        ParInh    <= not D_Int_In(20);
        EvenOdd_N <= not D_Int_In(21);
        SBSel     <=     D_Int_In(22);
    end process;
    

----------------------------------------------------------------------------
    UARTs_Quiet    <= TrHoRegEm_A and TrHoRegEm_B and TrSeRegEm_A and TrSeRegEm_B;

----------------------------------------------------------------------------
		Sync_Intr_UART: process(Reset_Int_N, Clk_Int)
		begin
		  if Reset_Int_N ='0' then
		  	TrSeRegEm_A_rck   <= '1';
		  	D_Ready_A_rck     <= '0';
		  	TrSeRegEm_B_rck   <= '1';
		  	D_Ready_B_rck     <= '0';
		  	Intr_UART_Err_rck <= '1';
		  
	  	elsif Clk_Int'event and Clk_Int = '1' then
		  	TrSeRegEm_A_rck   <= TrSeRegEm_A;
		  	D_Ready_A_rck     <= D_Ready_A;
		  	TrSeRegEm_B_rck   <= TrSeRegEm_B;
		  	D_Ready_B_rck     <= D_Ready_B;
		  	Intr_UART_Err_rck <= O_Err_A or Par_Err_A or Frame_Err_A or 
                             O_Err_B or Par_Err_B or Frame_Err_B;
		  end if;
		  
  	end process;
  		
	 TrSeRegEm_A_redge <= TrSeRegEm_A and not(TrSeRegEm_A_rck);
	 TrSeRegEm_B_redge <= TrSeRegEm_B and not(TrSeRegEm_B_rck);
	 
	 D_Ready_A_redge <= D_Ready_A and not(D_Ready_A_rck);
	 D_Ready_B_redge <= D_Ready_B and not(D_Ready_B_rck);
	 
   Intr_UARTA_Data <= (D_Ready_A_redge or TrSeRegEm_A_redge) and
                      not(Frame_Err_A or Par_Err_A or O_Err_A);
                      
   Intr_UARTB_Data <= (D_Ready_B_redge or TrSeRegEm_B_redge) and 
                      not(Frame_Err_B or Par_Err_B or O_Err_B);
  
   Intr_UART_Err   <= (O_Err_A or Par_Err_A or Frame_Err_A or 
                       O_Err_B or Par_Err_B or Frame_Err_B) and not Intr_UART_Err_rck;