meclibrary.vhd

ERC32 经典的sparc v7 cpu

WriteTransReg: process (MCK, MR)
begin
  if (MR = '1') then
   TransmitReg <= "1111111111";         -- shall be set to 1 
  elsif (MCK'event and MCK = '1') then  
     
    if LoadTransmitReg = '1' then
      TransmitReg(0) <= '0';             -- Start Bit
      TransmitReg(1) <= TransBufReg(0);  -- LSB
      TransmitReg(2) <= TransBufReg(1);  
      TransmitReg(3) <= TransBufReg(2);  
      TransmitReg(4) <= TransBufReg(3);  
      TransmitReg(5) <= TransBufReg(4);  
      TransmitReg(6) <= TransBufReg(5);  
      TransmitReg(7) <= TransBufReg(6);  
      TransmitReg(8) <= TransBufReg(7);  -- MSB
      if PIReg = '1' then    
         TransmitReg(9)  <= '1';        -- No parity (Stop Bit)
      elsif EPEReg = '1' then    
         TransmitReg(9) <= EmiPar;      -- Even Parity
      else
         TransmitReg(9) <= not EmiPar;  -- Odd Parity 
      end if;
      
     elsif  ShiftTransmitReg = '1' then
      TransmitReg(0)  <=  TransmitReg(1); 
      TransmitReg(1)  <=  TransmitReg(2); 
      TransmitReg(2)  <=  TransmitReg(3); 
      TransmitReg(3)  <=  TransmitReg(4); 
      TransmitReg(4)  <=  TransmitReg(5); 
      TransmitReg(5)  <=  TransmitReg(6); 
      TransmitReg(6)  <=  TransmitReg(7); 
      TransmitReg(7)  <=  TransmitReg(8); 
      TransmitReg(8)  <=  TransmitReg(9); 
      TransmitReg(9)  <=  '1';            -- furture stop bit

    end if;
  end if;
  
end process;

EmiPar <= TransBufReg(0) xor TransBufReg(1) xor TransBufReg(2) xor TransBufReg(3) xor
          TransBufReg(4) xor TransBufReg(5) xor TransBufReg(6) xor TransBufReg(7);
          

----------------------------------------------------------------------------
-- Emission FSM
-- 
EMIfsm1 : process(MCK, MR)
begin
  if(MR = '1') then
     SEmi <= ZD0;
  elsif (MCK'event and MCK = '1') then  
     SEmi <= Next_SEmi;
  end if;
end process;

EMIfsm2 : process(SEmi, LoadTransmitReg, EnCountClkEmi, TRC,
                  SetFlagTBRE, SBSReg, PIReg, FlagTBRE,
                  ZeroCountClkEmi)
begin

Next_SEmi <= SEmi;
LoadTransmitReg <= '0';
EnCountClkEmi   <= '0';
SetFlagTBRE     <= '0';
TREActive         <= '0';
TREStopBit      <= '0';

  case SEmi is
  -- Idle State
    when ZD0 =>
      if FlagTBRE = '0' and TRC = '1' then
        Next_SEmi <= ZD1;
      end if;
      TREActive <= '1';          -- Transmitted Register is empty
  
  -- Load Transmit Register
  -- Clear TRBL Flag
  -- Emit Start Bit 
    when ZD1 =>
      Next_SEmi <= ZD2;
      LoadTransmitReg <= '1';
      SetFlagTBRE     <= '1';
      EnCountClkEmi   <= '1';
      
  -- Continue to Emit Start Bit
  -- (used since LoadTransmitReg shall last only 1 MCK period)
    when ZD2 =>
      if TRC = '1' then   
        Next_SEmi <= ZD3;
      end if;
      EnCountClkEmi   <= '1';
      
         
  -- Start Bit Emission
    when ZD3 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD4;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 1
    when ZD4 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD5;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 2
    when ZD5 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD6;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 3
    when ZD6 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD7;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 4
    when ZD7 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD8;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 5
    when ZD8 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD9;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 6
    when ZD9 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD10;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 7
    when ZD10 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD11;
      end if;
      EnCountClkEmi   <= '1';
      
  -- data bit emission 8
    when ZD11 =>
      if ZeroCountClkEmi = '1' then
        if PIReg = '1' then
          if SBSReg = '0' then
            Next_SEmi <= ZD14;  -- no parity 1 stop bit jump to last stop bit
          else            
            Next_SEmi <= ZD13;  -- no parity 2 stop bits
          end if;
        else
          Next_SEmi <= ZD12;    -- parity
        end if;
      end if;
      EnCountClkEmi   <= '1';

  -- parity
    when ZD12 =>
      if ZeroCountClkEmi = '1' then
        if SBSreg = '0' then
          Next_SEmi <= ZD14;       -- 1 stop bit jump to last stop bit
        else       
          Next_SEmi <= ZD13;       -- 2 stop bits
        end if;
      end if;
      EnCountClkEmi   <= '1';

  -- first stop bit in case of 2 stop bits
    when ZD13 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD14;       -- 2 stop bits
      end if;
      EnCountClkEmi   <= '1';
      
  -- 2nd stop bit or 1st stop bit if only 1
    when ZD14 =>
      if ZeroCountClkEmi = '1' then       
        Next_SEmi <= ZD15;
      end if;
      TREStopBit      <= '1';       -- TRE is generated in this period
      EnCountClkEmi   <= '1';
      
  -- end state
  -- 
    when ZD15 =>
      if FlagTBRE = '0' then
        Next_SEmi <= ZD2;
        LoadTransmitReg <= '1';
        SetFlagTBRE     <= '1';
        EnCountClkEmi   <= '1';
      else
        Next_SEmi <= ZD0;
      end if;
      TREActive <= '1';          -- Transmitted Register is empty
       
    when others =>
      Next_SEmi <= ZD0;
    end case;
    
 
end process;





----------------------------------------------------------------------------
--RECEIVING PART
----------------------------------------------------------------------------
-- this counter is used to synchronize the data In sample w.r.t. the
-- receive clock RRC
-- The data is sampled when the counter is 0111 and RRC = 1
-- Resynchronization of RRI_R
--
ReceiveClk: process(MCK, MR)
begin
  if (MR = '1') then
    CountClkRec  <= "0000";
    RRI_R <= '1';
  
  elsif (MCK'event and MCK = '1') then
    if (EnCountClkRec = '0') then
      CountClkRec  <= "0000";
    elsif EnCountClkRec = '1' and RRC = '1' then
      CountClkRec <= CountClkRec + 1;
    end if;
    
    RRI_R <= RRI;
    
  end if;
end process;

ReceiveClk1: process(CountClkRec, RRC)
begin
   if RRC = '1' and CountClkRec = "0111" then
     SampleRec <= '1';
   else
     SampleRec <= '0';
   end if;
end process;


----------------------------------------------------------------------------
-- finite state for the receive part
-- this fsm starts upon receipt of a start bit
-- 
----------------------------------------------------------------------------
-- Emission FSM
-- 
RECfsm1 : process(MCK, MR)
begin
  if(MR = '1') then
     SRec <= ZD0;
  elsif (MCK'event and MCK = '1') then  
     SRec <= Next_SRec;
  end if;
end process;


RECfsm2: process(SRec, SampleRec, RRI_R,
                 PIReg, SBSReg, EPEReg)
begin

EnCountClkRec          <= '0';
DataBitSampled        <= '0';
StartBitSampled       <= '0';
ParBitSampled         <= '0';
FirstStopBitSampled   <= '0';
Next_SRec             <= Srec;

  case SRec is
  
  -- idle State
  -- waiting for start bit
   when ZD0 =>
     if RRI_R = '0' then
       Next_SRec <= ZD1;
     end if;
     
  -- start Counting
  -- falling edge detected on RRI_R
  -- and wait for middle of start bit
    when ZD1 => 
     if SampleRec = '1' then
       if RRI_R = '0' then
         Next_SRec <= ZD2;    -- ok start bit sampled at 0
       else
         Next_SRec <= ZD0;    -- wrong start bit
       end if;
       StartBitSampled <= '1';    -- init parity computation
     end if;
     EnCountClkRec <= '1';
     
  -- to middle of  data bit 1
    when ZD2 => 
     if SampleRec = '1' then
       Next_SRec <= ZD3;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  data bit 2
    when ZD3 => 
     if SampleRec = '1' then
       Next_SRec <= ZD4;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  data bit 3
    when ZD4  => 
     if SampleRec = '1' then
       Next_SRec <= ZD5;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  data bit 4
    when ZD5 => 
     if SampleRec = '1' then
       Next_SRec <= ZD6;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';

  -- to middle of  data bit 5
    when ZD6 => 
     if SampleRec = '1' then
       Next_SRec <= ZD7;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec    <= '1';
     
  -- to middle of  data bit 6
    when ZD7 => 
     if SampleRec = '1' then
       Next_SRec <= ZD8;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';
     
  -- to middle of  data bit 7
    when ZD8 => 
     if SampleRec = '1' then
       Next_SRec <= ZD9;
       DataBitSampled      <= '1';
     end if;
     EnCountClkRec <= '1';
     
  -- to middle of  data bit 8
    when ZD9 => 
     if SampleRec = '1' then
        if PIReg = '1' then
          Next_SRec <= ZD11;    -- no parity -> 1st stop bit
        else
          Next_SRec <= ZD10;    -- parity
        end if;