meclibrary.vhd

ERC32 经典的sparc v7 cpu

           2 => Chk_Ok(2) xor Chkbits_In(2),
           1 => Chk_Ok(1) xor Chkbits_In(1),
           0 => Chk_Ok(0) xor Chkbits_In(0) );
end ;

-------------------------------------------------------------------------
function Correct_Data ( Syndrom : in  SyndromBits;
                         Data   : in  Std_Logic_Vector ) return std_logic_vector is
begin
   case Syndrom is
      when "00111000" => return ( Data xor "000000000000000000000000000000001");
      when "01000101" => return ( Data xor "000000000000000000000000000000010");
      when "01010100" => return ( Data xor "000000000000000000000000000000100");
      when "00010110" => return ( Data xor "000000000000000000000000000001000");
      when "00011111" => return ( Data xor "000000000000000000000000000010000");
      when "00100101" => return ( Data xor "000000000000000000000000000100000");
      when "00100110" => return ( Data xor "000000000000000000000000001000000");
      when "01001010" => return ( Data xor "000000000000000000000000010000000");
      when "00101111" => return ( Data xor "000000000000000000000000100000000");
      when "00111011" => return ( Data xor "000000000000000000000001000000000");
      when "00111101" => return ( Data xor "000000000000000000000010000000000");
      when "01100001" => return ( Data xor "000000000000000000000100000000000");
      when "00011010" => return ( Data xor "000000000000000000001000000000000");
      when "00101010" => return ( Data xor "000000000000000000010000000000000");
      when "00101100" => return ( Data xor "000000000000000000100000000000000");
      when "01001111" => return ( Data xor "000000000000000001000000000000000");
      when "01000110" => return ( Data xor "000000000000000010000000000000000");
      when "01010010" => return ( Data xor "000000000000000100000000000000000");
      when "01100100" => return ( Data xor "000000000000001000000000000000000");
      when "01011101" => return ( Data xor "000000000000010000000000000000000");
      when "00100011" => return ( Data xor "000000000000100000000000000000000");
      when "00110001" => return ( Data xor "000000000001000000000000000000000");
      when "01001100" => return ( Data xor "000000000010000000000000000000000");
      when "01101000" => return ( Data xor "000000000100000000000000000000000");
      when "00010011" => return ( Data xor "000000001000000000000000000000000");
      when "00110010" => return ( Data xor "000000010000000000000000000000000");
      when "00110100" => return ( Data xor "000000100000000000000000000000000");
      when "01011000" => return ( Data xor "000001000000000000000000000000000");
      when "01000011" => return ( Data xor "000010000000000000000000000000000");
      when "01010001" => return ( Data xor "000100000000000000000000000000000");
      when "01011011" => return ( Data xor "001000000000000000000000000000000");
      when "01101101" => return ( Data xor "010000000000000000000000000000000");
      when "00000000" => return ( Data xor "100000000000000000000000000000000");
      when "10000000" => return ( Data xor "000000000000000000000000000000000");
      when others => if VecUnknown(syndrom) then
                        return  "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
                     else
                        return data;
                     end if;
   end case;
end Correct_Data;

------------------------------------------------------------------------
function NCError_Gen ( Syndrom : in  SyndromBits ) return std_logic is
begin
   case Syndrom is
     when "00111000" | "01000101" | "01010100" | "00010110" | "00011111" | "00100101" |
          "00100110" | "01001010" | "00101111" | "00111011" | "00111101" | "01100001" |
          "00011010" | "00101010" | "00101100" | "01001111" | "01000110" | "01010010" |
          "01100100" | "01011101" | "00100011" | "00110001" | "01001100" | "01101000" |
          "00010011" | "00110010" | "00110100" | "01011000" | "01000011" | "01010001" |
          "01011011" | "01101101" | "00000000" | "10000001" | "10000010" | "10000100" |
          "10001000" | "10010000" | "10100000" | "11000000" | "10000000" => return '0';
      when others => return '1';
   end case;
end NCError_Gen;

----------------------------------------------------------------------
function CError_Gen ( Syndrom : in  SyndromBits ) return std_logic is
begin
   case Syndrom is
     when "00111000" | "01000101" | "01010100" | "00010110" | "00011111" | "00100101" |
          "00100110" | "01001010" | "00101111" | "00111011" | "00111101" | "01100001" |
          "00011010" | "00101010" | "00101100" | "01001111" | "01000110" | "01010010" |
          "01100100" | "01011101" | "00100011" | "00110001" | "01001100" | "01101000" |
          "00010011" | "00110010" | "00110100" | "01011000" | "01000011" | "01010001" |
          "01011011" | "01101101" | "00000000" | "10000001" | "10000010" | "10000100" |
          "10001000" | "10010000" | "10100000" | "11000000" => return '1';
      when others =>     return '0';
   end case;
end CError_Gen;

end MECPackage;
---------------------------------------------------------------------------
--                Copyright MATRA MARCONI SPACE FRANCE                   --
---------------------------------------------------------------------------
--  The ownership and copyright of this document belong to               --
--  MATRA MARCONI SPACE FRANCE and it must not be disclosed, copied,     --
--  altered or used without the written                                  --
--  permission of MATRA MARCONI SPACE FRANCE.                            --
---------------------------------------------------------------------------
-- Title:                      UART component
-- File name:                  uart.vhd
-- VHDL unit:                  uart
-- Purpose and functionality:  
-- Reference:                  (RDx)
-- Analysis Dependencies:      (N/A)
-- Limitations:                (N/A)
-- Fidelity:                   (N/A)
-- Discrepancies:              (N/A)
-- Usage:                      (N/A)
-- I/O:                        (N/A)
-- Operations:                 (N/A)
-- Assertions:                 (N/A)
-- Development Platform:       (N/A)
-- Analyzer:                   (No Dependencies)
-- Synthesis:                  (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included)                            --
---------------------------------------------------------------------------
-- Version No:    Author:            Modification Date:    Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A    Remi CISSOU           1996-04-22           New issue
--
---------------------------------------------------------------------------
--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned."+";

entity uart is
port(
     MCK  : in std_logic;   -- Master clock provided
     TBR1 : in std_logic;   -- Transmitter Buffer Register (0)
     TBR2 : in std_logic;   -- Transmitter Buffer Register (1)
     TBR3 : in std_logic;   -- Transmitter Buffer Register (2)
     TBR4 : in std_logic;   -- Transmitter Buffer Register (3)
     TBR5 : in std_logic;   -- Transmitter Buffer Register (4)
     TBR6 : in std_logic;   -- Transmitter Buffer Register (5)
     TBR7 : in std_logic;   -- Transmitter Buffer Register (6)
     TBR8 : in std_logic;   -- Transmitter Buffer Register (7)
          
     TBRL_N : in std_logic;   -- Transmitter Buffer Register Load
     CRL  : in std_logic;   -- Control Register Load
     SBS  : in std_logic;   -- Stop Bit Select
          
     PI   : in std_logic;   -- Parity Inhibit
     EPE  : in std_logic;   -- Even Parity Enable (when PI is low)
          
     DRR  : in std_logic;   -- Data Received Reset
          
     TRC  : in std_logic;   -- Transmitter Register Clk
          
     RRC  : in std_logic;   -- Receiver Register Clk
          
     RRI  : in std_logic;   -- Receiver Register Input
          
     MR   : in std_logic;   -- Master Reset
          
     RBR1 : out std_logic;  -- Receiver Buffer Register (0)
     RBR2 : out std_logic;  -- Receiver Buffer Register (1)
     RBR3 : out std_logic;  -- Receiver Buffer Register (2)
     RBR4 : out std_logic;  -- Receiver Buffer Register (3)
     RBR5 : out std_logic;  -- Receiver Buffer Register (4)
     RBR6 : out std_logic;  -- Receiver Buffer Register (5)
     RBR7 : out std_logic;  -- Receiver Buffer Register (6)
     RBR8 : out std_logic;  -- Receiver Buffer Register (7)
          
     DR   : out std_logic;  -- Data Received
          
     TBRE : out std_logic;  -- Transmitter Buffer Register Empty
     TRE  : out std_logic;  -- Transmitter Register Empty
          
     FE   : out std_logic;  -- Frame Error
     PE   : out std_logic;  -- Parity Error
     OE   : out std_logic;  -- Overrun Error
          
     TRO  : out std_logic   -- Transmitter Register Output
     );
end uart;

architecture VHDL_RTL of uart is

 constant ZD0           : std_logic_vector(3 downto 0) := "0000";
 constant ZD1           : std_logic_vector(3 downto 0) := "0001";
 constant ZD2           : std_logic_vector(3 downto 0) := "0010";
 constant ZD3           : std_logic_vector(3 downto 0) := "0011";
 constant ZD4           : std_logic_vector(3 downto 0) := "0100";
 constant ZD5           : std_logic_vector(3 downto 0) := "0101";
 constant ZD6           : std_logic_vector(3 downto 0) := "0110";
 constant ZD7           : std_logic_vector(3 downto 0) := "0111";
 constant ZD8           : std_logic_vector(3 downto 0) := "1000";
 constant ZD9           : std_logic_vector(3 downto 0) := "1001";
 constant ZD10          : std_logic_vector(3 downto 0) := "1010";
 constant ZD11          : std_logic_vector(3 downto 0) := "1011";
 constant ZD12          : std_logic_vector(3 downto 0) := "1100";
 constant ZD13          : std_logic_vector(3 downto 0) := "1101";
 constant ZD14          : std_logic_vector(3 downto 0) := "1110";
 constant ZD15          : std_logic_vector(3 downto 0) := "1111";

 -- programmation registers 
 signal PIReg            : std_logic;       -- Parity inhbit
 signal EPEReg           : std_logic;       -- EvenParity Enable
 signal SBSReg           : std_logic;       -- 2 Stop bits detected

 -- Emission signals
 signal SEmi             : std_logic_Vector(3 downto 0); -- fsm state
 signal Next_SEmi        : std_logic_Vector(3 downto 0); -- next fsm state

 signal CountClkEmi      : std_logic_Vector(3 downto 0);  -- counter used to divide TRC by 16
 signal EnCountClkEmi    : std_logic;                     -- Enable of the CountClkEmi counter
 signal ZeroCountClkEmi  : std_logic;                     -- CountClkEmi = 0000 and TRC enable

 signal TransBufReg      : std_logic_Vector(7 downto 0);  -- temporary buffer register
 signal TransmitReg      : std_logic_Vector(9 downto 0);  -- Transmit Register
 signal LoadTransmitReg  : std_logic;                     -- load Transmit Reg
 signal ShiftTransmitReg : std_logic;                     -- shift Transmit Reg
 signal EmiPar           : std_logic;                     -- Emitted Parity
 signal FlagTBRE         : std_logic;                     -- A new Data is loaded in the Transmit
                                                         -- buffer register
 signal SetFlagTBRE      : std_logic;                     -- set Flag TBRE 

 signal TREActive        : std_logic;   -- active if fsm EMi in idle or end state
 signal TREStopBit       : std_logic;   -- active during last Stop Bit

 -- Reception Signals

 signal RRI_R            : std_logic;                     -- RRI after resynchro
 signal SRec             : std_logic_Vector(3 downto 0);  -- fsm state
 signal Next_SRec        : std_logic_Vector(3 downto 0);  -- next fsm state

 signal CountClkRec      : std_logic_Vector(3 downto 0);  --  Reception Clk Counter
 signal EnCountClkRec    : std_logic;                     -- Enable rec Clk counting

 signal DataBitSampled      : std_logic; --  Active when a data bit is received
 signal StartBitSampled     : std_logic; --  Active when start bit is received
 signal ParBitSampled       : std_logic; --  Active when Parity bit is received
 signal FirstStopBitSampled : std_logic; --  Active when 1st stop bit is received
 signal SampleRec           : std_logic; --  Active when data is sampled on RRI_R

 signal ParecReg         : std_logic;        -- parity received register
 signal PEReg            : std_logic;        -- Parity Error register
 signal OEReg            : std_logic;        -- Overrun  Error register      
 signal DRReg            : std_logic;        -- Data ready register      
 signal FEReg            : std_logic;        -- Frame  Error register      
  
 signal ReceiveReg       : std_logic_Vector(7 downto 0);   -- receive register    
 signal RecBufReg        : std_logic_Vector(7 downto 0);   -- receive buffer register


begin

----------------------------------------------------------------------------
--These outputs are used inside, too.
    TBRE  <= FlagTBRE;
-- TRE is generated when emi fsm is idle
-- or during the second half of the last stop bit
--
    TRE  <= TREActive or ( TREStopBit and not(CountClkEmi(3)) ) ;
    TRO  <= TransmitReg(0);

    RBR1 <= RecBufReg(0);
    RBR2 <= RecBufReg(1);
    RBR3 <= RecBufReg(2);
    RBR4 <= RecBufReg(3);
    RBR5 <= RecBufReg(4);
    RBR6 <= RecBufReg(5);
    RBR7 <= RecBufReg(6);
    RBR8 <= RecBufReg(7);
    
    FE   <= FEReg;
    OE   <= OEReg;
    DR   <= DRReg;
    PE   <= PEReg;



----------------------------------------------------------------------------
-- Programming part
-- Synchronous Memorization of the parity, number of stop bits
-- upon receipt of the CRL signal compliant with the MCK clock
----------------------------------------------------------------------------
WriteControlRegister: process(MCK, MR)
begin
  if (MR = '1') then    
    PIReg      <= '0';
    EPEReg     <= '0';
    SBSReg     <= '0';
  
  elsif (MCK'event and MCK = '1') then
    -- when PI  = 0 and EPE = 1 => parity EVEN
    -- when PI  = 0 and EPE = 0 => parity ODD
    -- when PI  = 1 and EPE = x => no parity, PE = 0
    -- when SBS = 0             => 1 stop bit
    -- when SBS = 1             => 2 stop bits
    if CRL = '1' then
      PIReg  <= PI;
      EPEReg <= EPE;
      SBSReg <= SBS;
    end if;
  end if;
end process;


----------------------------------------------------------------------------
--Transmitting part
----------------------------------------------------------------------------
-- This counter is used to divide the TRC input by 16 to generate pulses on
-- TRO
-- It starts upon activation of EnCountClkEmi by the Emission fsm
-- It counts each time a TRC pulse is received
--
-- The ShiftTransmitReg shifts the transmission buffer in emission
-- one clock period after CountClkEmi = 0000 and TRC = '1'
--
TransmitClock: process(MCK, MR)
begin
  if (MR = '1') then
    CountClkEmi  <= ZD15 ;
    ShiftTransmitReg <= '0';

  elsif (MCK'event and MCK = '1') then
    if EnCountClkEmi = '0' then
        CountClkEmi <=  ZD15;         
    elsif EnCountClkEmi = '1' and TRC = '1' then 
        CountClkEmi <= CountClkEmi - 1;
    end if;
    
    ShiftTransmitReg <= ZeroCountClkEmi;
  end if;
end process;

ZeroCountClkEmi <= '1' when CountClkEmi = ZD0 and TRC = '1' else '0';

----------------------------------------------------------------------------
-- Synchronous load of the transmit buffer register
-- on receipt of TBRL signal
-- A Flag is reset to indicate that the TB Register is not empty
--
WriteTransBufReg: process (MCK, MR)
begin
  if (MR = '1') then
   FlagTBRE <= '1';
   TransBufReg <= "00000000";
  elsif (MCK'event and MCK = '1') then     
    if TBRL_N = '0' then
      TransBufReg(7) <= TBR8;
      TransBufReg(6) <= TBR7;
      TransBufReg(5) <= TBR6;
      TransBufReg(4) <= TBR5;
      TransBufReg(3) <= TBR4;
      TransBufReg(2) <= TBR3;
      TransBufReg(1) <= TBR2;
      TransBufReg(0) <= TBR1;
      FlagTBRE <= '0';          -- a new data to emit is received
    end if;
    if SetFlagTBRE = '1' then
      FlagTBRE <= '1';          -- TB Register empty
    end if;
    
  end if; 
end process;



----------------------------------------------------------------------------
-- Synchronous load of the transmit register by the fsm
-- Start bit, parity and stop bit values are added 
-- Synchronous shift of the register
--
-- There is a trick with the TransmitReg register
-- its size is only 10 bits ( 1 start bit + 8 data + parity )
-- the stop bit at 1 is generated by inputing 1 
-- in bit 9 of the register !!
--