meclibrary.vhd

ERC32 经典的sparc v7 cpu

---------------------------------------------------------------------------
--                Copyright SAAB ERICSSON SPACE AB                       --
---------------------------------------------------------------------------
 
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Library General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
 
--  This library is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--  Library General Public License for more details.
 
--  You should have received a copy of the GNU Library General Public
--  License along with this library; if not, write to the Free
--  Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

---------------------------------------------------------------------------
-- Title:
-- File name:
-- VHDL unit:                  (Type)
-- Purpose and functionality:  (Text)
-- Reference:                  (RDx)
-- Analysis Dependencies:      (N/A)
-- Limitations:                (N/A)
-- Fidelity:                   (N/A)
-- Discrepancies:              (N/A)
-- Usage:                      (N/A)
-- I/O:                        (N/A)
-- Operations:                 (N/A)
-- Assertions:                 (N/A)
-- Development Platform:       (N/A)
-- Analyzer:                   (No Dependencies)
-- Synthesis:                  (No Dependencies)
---------------------------------------------------------------------------
-- Revision history: (all revisions included)                            --
---------------------------------------------------------------------------
-- Version No:    Author:            Modification Date:    Changes made: --
---------------------------------------------------------------------------
-- v1.0 Rev A    Remi CISSOU           1996-04-22           New issue
--
---------------------------------------------------------------------------
--  SAAB ERICSSON SPACE AB                                               --
--  Delsjomotet                      Phone Int: [phone]          --
--  S-405 15 GOTHENBURG              Fax   Int: [phone]          --
--  Sweden                           Telex:     27950 saabsp s           --
---------------------------------------------------------------------------
 

--
--

library IEEE;
use IEEE.Std_Logic_1164.all;

library MMS;
use MMS.StdRTL.all;

package MECPackage is

    type UX01_Vector is array (natural range <>) of UX01;

--- Subtype used in the EDAC
   subtype CheckBits   is std_logic_Vector ( 6 downto 0 );
   subtype SyndromBits is std_logic_Vector ( 7 downto 0 );
   subtype DataBits    is std_logic_Vector ( 31 downto 0 );

    function ParityGen(Val : Std_Logic_Vector) return UX01;

    function ParityCheck(Val: Std_Logic_Vector; Parity: UX01)
                         return UX01;

    function Decrement(Val : Std_Logic_Vector) return Std_Logic_Vector;

--    function Hex2Vec(HexInput: string; Width: positive)
--                     return Std_Logic_Vector;

--    function To_UX01_Vector (Input: Std_Logic_Vector)
--                             return UX01_vector;
-- This function is not used and therfore removed

    function Bool_To_UX01 (Val : Boolean) return UX01;

    function Vector_OR ( Data : Std_Logic_Vector ) return UX01;

--    function Bit_And_Vector ( Bit : UX01; Vec : Std_Logic_Vector) return Std_Logic_Vector;
-- This function is not used and therfore removed

    function Compare (A,B : Std_Logic_Vector) return UX01;

    --- Generate check bits
    function ChkGen ( Data : in DataBits ) return CheckBits;

    --- Generate syndrom bits
    function SyndromGen ( ChkBits_In : CheckBits;
                          Chk_Ok     : CheckBits;
                          Parity     : std_logic ) return SyndromBits;

    function SyndromGenS ( ChkBits_In : CheckBits;
                           Chk_Ok     : CheckBits;
                           Chk_Ok7    : std_logic;
                           Parity     : std_logic ) return SyndromBits;
                           
                       
     function Correct_Data ( Syndrom : in  SyndromBits;
                             Data   : in  Std_logic_vector ) return std_logic_vector;

     function NCError_Gen ( Syndrom : in  SyndromBits ) return std_logic;

     function CError_Gen ( Syndrom : in  SyndromBits ) return std_logic;

end MECPackage;

---------------------------------------------------------------------------
package body MECPackage is

    type Logic_UX01_Table is array (Std_ulogic'low to Std_ulogic'high) of UX01;

    constant Cvt_To_UX01 : Logic_UX01_Table := (
                         'U',  -- 'U'
                         'X',  -- 'X'
                         '0',  -- '0'
                         '1',  -- '1'
                         'X',  -- 'Z'
                         'X',  -- 'W'
                         '0',  -- 'L'
                         '1',  -- 'H'
                         'X'   -- '-'
                        );

---------------------------------------------------------------------------
    function ParityGen(Val : Std_Logic_Vector) return UX01 is

        --Normalize the indexing
        alias Data     : Std_Logic_Vector(Val'length downto 1) is Val;
        variable Result : UX01 := '1';
    begin
        for K in 1 to Data'length loop
            Result := Result xor Data(K);
        end loop;
        return Result;
    end ParityGen;

---------------------------------------------------------------------------
    function ParityCheck(Val: Std_Logic_Vector; Parity: UX01)
                                               return UX01 is

        --Normalize the indexing
        alias Data     : Std_Logic_Vector(Val'length downto 1) is Val;
        variable Result : UX01 := '1';
    begin
        for K in 1 to Data'length loop
            Result :=  Result xor Data(K);
        end loop;
        return (Result xor Parity);
    end ParityCheck;

---------------------------------------------------------------------------
    function Decrement(Val : Std_Logic_Vector) return Std_Logic_Vector is

        -- normalize the indexing
        alias Input     : Std_Logic_Vector(Val'length downto 1) is Val;
        variable Result : Std_Logic_Vector(Input'range) := Input;
    begin
        for K in 1 to Input'length loop
            Result(K) := not Input(K);
            exit when Input(K) = '1';
        end loop;
        return Result;
    end Decrement;

---------------------------------------------------------------------------
--    function Hex2Vec(HexInput: string; Width: positive)
--             return Std_Logic_Vector is
--
--        -- normalize the indexing
--        alias Hex : String(HexInput'length downto 1) is HexInput;
--        variable Temp   : Std_Logic_Vector(HexInput'length*4 downto 0)
--                          := (others => '0');
--        variable Result : Std_Logic_Vector(Width-1 downto 0)
--                          := (others => '0');
--        variable J,K : natural;
--    begin
--
--        J := 0;
--
--        for K in 1 to HexInput'length loop
--
--            if not (Hex(K) = '_') then
--
--                case Hex(K) is
--                    when '0'     => Temp(J+3 downto J) := "0000";
--
--                    when '1'     => Temp(J+3 downto J) := "0001";
--
--                    when '2'     => Temp(J+3 downto J) := "0010";
--
--                    when '3'     => Temp(J+3 downto J) := "0011";
--
--                    when '4'     => Temp(J+3 downto J) := "0100";
--
--                    when '5'     => Temp(J+3 downto J) := "0101";
--
--                    when '6'     => Temp(J+3 downto J) := "0110";
--
--                    when '7'     => Temp(J+3 downto J) := "0111";
--
--                    when '8'     => Temp(J+3 downto J) := "1000";
--
--                    when '9'     => Temp(J+3 downto J) := "1001";
--
--                    when 'a'|'A' => Temp(J+3 downto J) := "1010";
--
--                    when 'b'|'B' => Temp(J+3 downto J) := "1011";
--
--                    when 'c'|'C' => Temp(J+3 downto J) := "1100";
--
--                    when 'd'|'D' => Temp(J+3 downto J) := "1101";
--
--                    when 'e'|'E' => Temp(J+3 downto J) := "1110";
--
--                    when 'f'|'F' => Temp(J+3 downto J) := "1111";
--
--                    when others  => Temp(J+3 downto J) := "XXXX";
--                end case;
--
--                J := J+4;
--
--            end if;
--        end loop;
--
--        Result := Temp(Width-1 downto 0);
--        return Result;
--
--    end Hex2Vec;
--
---------------------------------------------------------------------------
    function Bool_To_UX01 (Val : Boolean) return UX01 is
    begin
      if Val then
        return '1';
      else
        return '0';
      end if;
    end;

--------------------------------------------------------------------------------
    function Vector_OR ( Data : Std_Logic_Vector ) return UX01 is
      variable Result : UX01 := '0';
    begin
      for K in Data'low to Data'high loop
        Result :=  Result or Data(K);
      end loop;
      return Result;
    end;

---------------------------------------------------------------------------
    function Compare (A,B : Std_Logic_Vector) return UX01 is
      variable xor_vector : Std_Logic_Vector(A'Length downto 1);
      variable result : UX01 := '0';
    begin
      -- assume that the length of A and B is equal
      xor_vector := A xor B;
      return Vector_OR (xor_vector);
    end;

---------------------------------------------------------------------------
 function ChkGen ( Data : in DataBits ) return CheckBits is

  alias D31 : std_logic is Data(31);
  alias D30 : std_logic is Data(30);
  alias D29 : std_logic is Data(29);
  alias D28 : std_logic is Data(28);
  alias D27 : std_logic is Data(27);
  alias D26 : std_logic is Data(26);
  alias D25 : std_logic is Data(25);
  alias D24 : std_logic is Data(24);
  alias D23 : std_logic is Data(23);
  alias D22 : std_logic is Data(22);
  alias D21 : std_logic is Data(21);
  alias D20 : std_logic is Data(20);
  alias D19 : std_logic is Data(19);
  alias D18 : std_logic is Data(18);
  alias D17 : std_logic is Data(17);
  alias D16 : std_logic is Data(16);
  alias D15 : std_logic is Data(15);
  alias D14 : std_logic is Data(14);
  alias D13 : std_logic is Data(13);
  alias D12 : std_logic is Data(12);
  alias D11 : std_logic is Data(11);
  alias D10 : std_logic is Data(10);
  alias D09 : std_logic is Data(9);
  alias D08 : std_logic is Data(8);
  alias D07 : std_logic is Data(7);
  alias D06 : std_logic is Data(6);
  alias D05 : std_logic is Data(5);
  alias D04 : std_logic is Data(4);
  alias D03 : std_logic is Data(3);
  alias D02 : std_logic is Data(2);
  alias D01 : std_logic is Data(1);
  alias D00 : std_logic is Data(0);

begin
  return (
  0 => D31 xor D30 xor D29 xor D28 xor D24 xor D21 xor D20 xor D19 xor
        D15 xor D11 xor D10 xor D09 xor D08 xor D05 xor D04 xor D01,

  1 => D30 xor D28 xor D25 xor D24 xor D20 xor D17 xor D16 xor D15 xor
        D13 xor D12 xor D09 xor D08 xor D07 xor D06 xor D04 xor D03,

  2 => not (D31 xor D26 xor D22 xor D19 xor D18 xor D16 xor D15 xor D14 xor
        D10 xor D08 xor D06 xor D05 xor D04 xor D03 xor D02 xor D01),

  3 => D31 xor D30 xor D27 xor D23 xor D22 xor D19 xor D15 xor D14 xor
        D13 xor D12 xor D10 xor D09 xor D08 xor D07 xor D04 xor D00,

  4 => not (D30 xor D29 xor D27 xor D26 xor D25 xor D24 xor D21 xor D19 xor
        D17 xor D12 xor D10 xor D09 xor D04 xor D03 xor D02 xor D00),

  5 => D31 xor D26 xor D25 xor D23 xor D21 xor D20 xor D18 xor D14 xor
        D13 xor D11 xor D10 xor D09 xor D08 xor D06 xor D05 xor D00,

  6 => D31 xor D30 xor D29 xor D28 xor D27 xor D23 xor D22 xor D19 xor

        D18 xor D17 xor D16 xor D15 xor D11 xor D07 xor D02 xor D01  );
 end;

---------------------------------------------------------------------------
---- 'ChkBits_In' are the checkbits read from the memory
---- 'Chk_Ok' are the checkbits generated from the data read from memory
---- 'Parity' is the parity read from the memory
function SyndromGenS ( ChkBits_In : CheckBits;
                       Chk_Ok     : CheckBits;
                       Chk_Ok7    : std_logic;
                       Parity     : std_logic ) return SyndromBits is
  
begin
        -- One can generate a parity bit from the word instead of
        -- using the generated checkbits as here
	return (
	   7 => Chk_Ok7 xor Parity,
	   6 => Chk_Ok(6) xor Chkbits_In(6),
	   5 => Chk_Ok(5) xor Chkbits_In(5),
	   4 => Chk_Ok(4) xor Chkbits_In(4),
	   3 => Chk_Ok(3) xor Chkbits_In(3),
	   2 => Chk_Ok(2) xor Chkbits_In(2),
	   1 => Chk_Ok(1) xor Chkbits_In(1),
	   0 => Chk_Ok(0) xor Chkbits_In(0) );
end ;


function SyndromGen ( ChkBits_In : CheckBits;
                      Chk_Ok     : CheckBits;
                      Parity     : std_logic ) return SyndromBits is

begin
        -- One can generate a parity bit from the word instead of
        -- using the generated checkbits as here
        return (
           7 => Chk_Ok(6) xor Chk_Ok(5) xor not(Chk_Ok(4)) xor    --gb 950527 bit 4 inverted
                Chk_Ok(3) xor not(Chk_Ok(2)) xor Chk_Ok(1) xor    --gb 950527 bit 4 inverted
                Chk_Ok(0) xor Parity,
           6 => Chk_Ok(6) xor Chkbits_In(6),
           5 => Chk_Ok(5) xor Chkbits_In(5),
           4 => Chk_Ok(4) xor Chkbits_In(4),
           3 => Chk_Ok(3) xor Chkbits_In(3),