iurt_lib.vhd

ERC32 经典的sparc v7 cpu

    variable WR3 : Instruction;
        
    -- Declaration of data objects for trap handling  
    variable TrapVector : TrapVectorType;
    variable NextAddressForTraps : std_logic_vector(31 downto 0); -- Addr. to be
                                                                  -- put in r18.
    variable Preserve_SavePrevAddr : std_logic_vector(31 downto 0); 
                                -- Save value to be put in r18 in certain cases
    
    -- Data objects for "anticipated" execution of OPcc instructions.
    variable ResultOpcc : std_logic_vector(31 downto 0); -- computed result
    variable iccTemp    : std_logic_vector(3 downto 0);  -- modified temp. icc
    variable YTemp      : std_logic_vector(31 downto 0); -- Temporary Y reg.
            
    -- Data objects for STORE instructions.
    variable StoreData : std_logic_vector(31 downto 0);
    variable DestReg   : natural;
    
    -- Data object for LOAD instructions.
    variable LoadDataAddr : std_logic_vector(31 downto 0);
    
    -- Data object for SWAP instructions
    variable SwapData : std_logic_vector(31 downto 0);
    
    -- Variables used for proper address generation when data cache miss or 
    -- memory exception bus hold.
    variable LDdataAD1 : std_logic_vector(31 downto 0);
    
    -- Flag for branches (Bicc, FBfcc)
    variable TakenBr : boolean := FALSE; -- Taken branch flag.

    -- Variables for output signals: corresponding signal name is just before
    -- "var" in variable name.
    -- pSIGNALvar = value of SIGNAL in previous cycle.
    -- pTOpSIGNALvar = value of SIGNAL in the cycle before the previous cycle.
    variable ASIvar       : natural; 
    variable pASIvar      : natural; 
    variable pTOpASIvar   : natural;
    variable SizeVar      : natural;
    variable pSizeVar     : natural;
    variable pTOpSizeVar  : natural;
    variable INTACKvar    : std_logic; 
    variable pINTACKvar   : std_logic; 
    variable ERROR_Nvar   : std_logic;
    variable RDvar        : std_logic;
    variable pRDvar       : std_logic;
    variable pTOpRDvar    : std_logic;
    variable WE_Nvar      : std_logic; 
    variable pWE_Nvar     : std_logic;
    variable pTOpWE_Nvar  : std_logic;
    variable WRTvar       : std_logic;
    variable pWRTvar      : std_logic;
    variable pTOpWRTvar   : std_logic;
    variable DXFERvar     : std_logic;
    variable pDXFERvar    : std_logic;
    variable pTOpDXFERvar : std_logic;
    variable LDSTOvar     : std_logic;
    variable pLDSTOvar    : std_logic;
    variable pTOpLDSTOvar : std_logic;
    variable INULLvar     : std_logic;
    variable pINULLvar    : std_logic;
    variable LOCKvar      : std_logic;
    variable pLOCKvar     : std_logic;
    variable pTOpLOCKvar  : std_logic;
    variable INSTvar      : std_logic;
    variable pINSTvar     : std_logic;
    variable FLUSHvar     : std_logic;
    variable pFLUSHvar    : std_logic;
    variable FXACKvar     : std_logic;
    variable pFXACKvar    : std_logic;
    variable FINS1var     : std_logic;
    variable pFINS1var    : std_logic;
    variable FINS2var     : std_logic;
    variable pFINS2var    : std_logic;
    variable HWERROR_Nvar  : std_logic;    
    variable pHWERROR_Nvar : std_logic;
    
    -- Flag for INTACK, FLUSH, FXACK signals
    variable TriggerINTACK : boolean := FALSE;
    variable TriggerFXACK  : boolean := FALSE;
    variable TriggerFLUSH  : boolean := FALSE;
    
    -- Variables for input signals: IRL bus, MDS_N
    variable IRLvar    : natural;
    variable pIRLvar   : natural;
    variable MDS_Nvar   : std_logic;
    variable MEXC_Nvar  : std_logic;
    variable FEXC_Nvar  : std_logic;
    variable FCCVvar    : std_logic;
    variable FHOLD_Nvar : std_logic;
      
    -- Variable to freeze the pipeline
    variable FrozenPipe : boolean := FALSE;
    
    -- Flags related to ERROR or RESET mode.
    variable FrozenBusses : boolean := TRUE; -- TRUE when in RESET_MODE except
                                             -- for the 1st clock cycle of reset
    variable ResetHasBeenDetected : boolean := FALSE;
    variable LocalCounterDuringReset : integer := -1;
    variable GenerateASIsig   : boolean := FALSE;
    variable GenerateERRORsig : boolean := FALSE;
    variable TrigERRcountdown : integer := -1;
    
    -- Master/Checker related variable
    variable CMDmismatch : natural := 0;

    -- Variable for Memory access exceptions
    variable PendingInstAccExc : integer := -2;

    -- Variables for Program Flow Control Scheme
    variable Checksum  : std_logic_vector(31 downto 0);
    variable CHKSUMsig : std_logic_vector(15 downto 0);
    variable ChecksumCompare : boolean;
        
    -- Variables for parity bit checking
    variable ParBitViolCount : integer := -1;
    variable DPARviol        : boolean := FALSE;
    variable FIPARviol       : boolean := FALSE;

    -- Other variables 
    variable Vec8bits : std_logic_vector(7 downto 0);
    variable Vec2bits : std_logic_vector(1 downto 0);
    variable PendingERROR : boolean := FALSE;
    variable TempINST : Instruction;
    
  begin
    ------ The body of this "if" statement is executed only once ------
    ------ for initialization purposes.                          ------
    if PowerUP then
      PowerUP := FALSE;
      
      RegFile(0) := (others => '0'); -- Global register zero.
                                     -- This register should NEVER be written.

      impl := PSR_IMPL; -- These bits are not affected by a WRPSR. They should
                        -- NOT be affected by a write.
                        
      ver  := PSR_VER; -- These bits are not affected by a WRPSR. They should
                       -- NOT be affected by a write.

      TBR(3 downto 0) := TBR3_DOWNTO_0; -- These bits are always 0. They should
                                 -- NOT be affected by a write.
                                 
      for i in NWINDOWS to 31 loop
        WIM(i) := '0'; -- Unimplemented windows are read as ZEROS and not 
      end loop;        -- affected by WRWIM.
      
      -- Checking timing parameters.
      if tAH >= tAD then
        assert FALSE report "[IURTGeneric(Behave)]: parameter tAD must be " &
                             "greater than tAH after re-computation!"
                      severity failure;
      end if;
   
      if tXAPH >= tXAPD then
        assert FALSE report "[IURTGeneric(Behave)]: parameter tXAPD must be " &
                             "greater than tXAPH after re-computation!"
                      severity failure;
      end if;
   
      if tDOH >= tDOD then
        assert FALSE report "[IURTGeneric(Behave)]: parameter tDOD must be " &
                             "greater than tDOH after re-computation!"
                      severity failure;
      end if;
   
      if tDPOH >= tDPOD then
        assert FALSE report "[IURTGeneric(Behave)]: parameter tDPOD must be " &
                             "greater than tDPOH after re-computation!"
                      severity failure;
      end if;
   
      if tIMPH >= tIMPD then
        assert FALSE report "[IURTGeneric(Behave)]: parameter tIMPD must be " &
                             "greater than tIMPH after re-computation!"
                      severity failure;
      end if;
   
      if tIFPH >= tIFPD then
        assert FALSE report "[IURTGeneric(Behave)]: parameter tIMPD must be " &
                             "greater than tIMPH after re-computation!"
                      severity failure;
      end if;
   
    end if;
    -------------------------------------------------------------------

    wait on CLK,
            MHOLDA_N, MHOLDB_N, BHOLD_N, MAO, FHOLD_N, FCCV,
            MHOLDA_Nlat, MHOLDB_Nlat, BHOLD_Nlat, FHOLD_Nlat, FCCVlat,
            HOLDsig_N,
            TOE_N,
            DTHCsig, ATHCsig, CTHCsig, ACTHCsig, THCsig,
            Ain, APARin, ASIin, Din, DPARin, DXFERin, INULLin, LDSTOin, LOCKin,
            RDin, SIZEin, ASPARin, WE_Nin, WRTin, IMPARin, FINS1in, FINS2in,
            FLUSHin, FXACKin, INSTin, IFPARin, INTACKin, ERROR_Nin, HWERROR_Nin,
            MCERR_Nin;
    
    
    ---- The 3 possible modes for the IU ----
    case Mode is
      when ERROR_MODE   =>        
        FrozenBusses := TRUE;
        if rising_edge(CLK) then
          if TrigERRcountdown = 0 then
            GenerateERRORsig := TRUE;
            ERROR_Nvar := '0';
            TrigERRcountdown := TrigERRcountdown - 1;
          elsif TrigERRcountdown > 0 then
            TrigERRcountdown := TrigERRcountdown - 1;
          end if;
        end if;
        
      when RESET_MODE   => 
        if ResetHasBeenDetected = TRUE then
          FrozenBusses := TRUE;
        end if;
        
        if (rising_edge(CLK) and Reset_N = '1'and not(StartUp)) then 
          Mode := EXECUTE_MODE; -- reset trap serviced here.
          TrapVector(RESET_TRAP)    := FALSE;
          TrapVector(DETECTED_TRAP) := FALSE;
          FrozenBusses := FALSE;
          ResetHasBeenDetected := FALSE;
          S  := '1';
          ET := '0';
          pINSTvar  := INSTvar;
          INSTvar   := '1'; -- First word on the bus is an instruction.
          pINULLvar := INULLvar;
          INULLvar  := '0';
          PrevAddr  := CurrentAddr;
          CurrentAddr := CurrentAddr + 4;
          
          CheckTimBidir <= TRUE; -- destined to the conditional timing checkers
          
        end if;
        
      when EXECUTE_MODE =>
      
      --------------------------------------------
      -- Only purpose of this: setup/hold timing checkers
      if rising_edge(CLK) then
        if EX.Mnemo = LDFSR or EX.Mnemo = LDF or WR.Mnemo = LDDF or 
           IsStoreInst(EX.Mnemo) or IsStoreInst(WR.Mnemo) or 
           IsStoreDoubleInst(WR1.Mnemo) or 
           WR.Mnemo = LDSTUB or WR.Mnemo = LDSTUBA or 
           WR1.Mnemo = LDSTUB or WR1.Mnemo = LDSTUBA or
           WR.Mnemo = SWAP or WR.Mnemo = SWAPA or 
           WR1.Mnemo = SWAP or WR1.Mnemo = SWAPA then
          CheckTimBidir <= FALSE;
        else
          CheckTimBidir <= TRUE;
        end if;
      end if;
      --------------------------------------------
      
      --^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
        if (rising_edge(CLK) and not(FrozenPipe)) then
          --.... Actions related to WRite (and WR1) stage(s) of pipeline ....
          DataFetchForLoadAndLdstInst(LoadDataAddr, D, CWP, WR, WR1,
                                      RegFile, 
                                      SwapData);          
           
      
          --......... Actions related to EXecute stage of pipeline ..........
          ExecutionBody(FP_N, IFT_N,
                        EX, ResultOpcc, YTemp, iccTemp,
                        Y, PSR, TBR, WIM, RegFile, Mode,
                        TrapVector);
                        
          --..... Evaluates latched FEXC_N pin for FP exceptions ............
          --..... A FP trap is recognized as a FP instr. goes into ..........
          --..... EX stage (ID.Mnemo is a FP instruction) TBC ...............
          if FEXC_Nvar = '0' and IsFPinst(EX.Mnemo) and FP_N = '0' then
            TrapVector(DETECTED_TRAP) := TRUE;
            TrapVector(FP_EXCEPTION)  := TRUE;
          end if;

          --....... Program Flow Control scheme .......
          if FLOW_N = '0' then
            if EX.Mnemo = SETHI and EX.rd = 0 then
              if EX.disp22 = 0 then
                ChecksumCompare := FALSE; -- disable next checksum comparison.
              elsif ChecksumCompare then
                CHKSUMsig := Checksum(31 downto 16) xor Checksum(15 downto 0);
                if EX.BitInstr(21 downto 16) = "011111" and 
                   CHKSUMsig /= EX.BitInstr(15 downto 0) then
                  TrapVector(DETECTED_TRAP)    := TRUE;
                  TrapVector(PROGRAM_FLOW_ERR) := TRUE;
                end if;
              elsif not(ChecksumCompare) then
                ChecksumCompare := TRUE;
              end if;
              Checksum := (others => '0'); -- zero checksum.
            elsif EX.Mnemo /= IOP and EX.Mnemo /= ANNULLED and 
                  EX.Mnemo /= NOTHING then
              Checksum := CheckSum xor EX.BitInstr(31 downto 0);
              if EX.Mnemo = RETT then
                ChecksumCompare := FALSE; -- disable next checksum comparison.
              end if;
            end if;
          end if;

          --....... Parity bit checking --> generate hardware error .......
          -- WARNING: fuzzy behavior of signal HWERROR_N.
          -- What if violation while on HOLD???
          -- Should there be a violation on DPAR when LDFSR, LDF or LDDF???
          if N601MODE_N = '1' then
            if ParBitViolCount = 1 and EX.Mnemo /= IOP then
              TrapVector(DETECTED_TRAP) := TRUE; 
              if DPARviol then