iurt_lib.vhd

来自「ERC32 经典的sparc v7 cpu」· VHDL 代码 · 共 1,551 行 · 第 1/5 页

package IURTTimPar is

  constant tCY    : time := 40 ns;
  constant tCHL   : time := 18 ns;
  constant tAD    : time := 33 ns; 
  constant tAH    : time := 16 ns;
  constant tDOD   : time := 29 ns;
  constant tDOH   : time :=  9 ns; 
  constant tDIS   : time :=  3 ns; 
  constant tDIH   : time :=  4 ns;
  constant tMES   : time := 15 ns;
  constant tMEH   : time :=  2 ns;
  constant tHS    : time :=  7 ns;
  constant tHH    : time :=  4 ns;
  constant tHOD   : time := 22 ns;
  constant tHOH   : time :=  8 ns; -- WARNING:
                                   -- For tHOH, the IURT spec. gives 0 ns.
                                   -- This does not seem to be compatible with
                                   -- the FPURT spec. for the hold time on A 
                                   -- bus (6 ns).
  constant tOE    : time := 15 ns;
  constant tOD    : time := 15 ns;
  constant tTOE   : time := 21 ns;
  constant tTOD   : time := 21 ns;
  constant tSSD   : time := 20 ns;
  constant tSSH   : time :=  7 ns;
  constant tRS    : time := 15 ns;
  constant tRH    : time :=  3 ns;
  constant tFD    : time := 27 ns;
  constant tFH    : time :=  9 ns;
  constant tFIS   : time := 10 ns;
  constant tFIH   : time :=  4 ns;
  constant tDXD   : time := 28 ns;
  constant tDXH   : time :=  5 ns;
  constant tHDXD  : time := 20 ns;
  constant tHDXH  : time :=  6 ns;-- WARNING:
                                   -- For tHDXH, the IURT spec. gives 0 ns.
                                   -- This does not seem to be compatible with
                                   -- the MEC spec. for the hold time on DXFER.
  constant tNUD   : time := 20 ns;
  constant tNUH   : time :=  7 ns;
  constant tMDS   : time :=  5 ns;
  constant tMDH   : time :=  4 ns;
  constant tFLS   : time := 15 ns;
  constant tFLH   : time :=  7 ns;
  constant tCCVS  : time :=  7 ns;
  constant tCCVH  : time :=  4 ns;
  constant tXES   : time := 10 ns;
  constant tXEH   : time :=  4 ns;
  constant tMAD   : time := 20 ns; 
  constant tMAH   : time :=  5 ns;
  constant tETD   : time := 25 ns;
  constant tETH   : time :=  7 ns;
  constant tXAPD  : time := 33 ns;
  constant tXAPH  : time := 16 ns;
  constant tDPOD  : time := 29 ns;
  constant tDPOH  : time :=  9 ns;
  constant tDPIS  : time :=  3 ns;
  constant tDPIH  : time :=  4 ns;
  constant tIFPD  : time := 29 ns;
  constant tIFPH  : time :=  7 ns;
  constant tFIPS  : time := 10 ns;
  constant tFIPH  : time :=  4 ns;
  constant tIMPD  : time := 33 ns;
  constant tIMPH  : time := 16 ns;
  constant tMCED  : time := 15 ns;
  constant tMCEV  : time :=  7 ns;
  constant tSTATS : time := 10 ns;
  constant tHAS   : time :=  7 ns;
  constant tHAH   : time :=  4 ns;
  constant tHAE   : time := 14 ns; -- instead of 18
  constant tHAD   : time := 14 ns; -- instead of 18
   
  constant tTCY   : time := 100 ns;  
  constant tTMS   : time := 20 ns;  
  constant tTMH   : time :=  4 ns;  
  constant tTDIS  : time := 20 ns;  
  constant tTDIH  : time :=  4 ns;  
  constant tTRS   : time := 20 ns;  
  constant tTRH   : time :=  4 ns;  
  constant tTDOD  : time := 30 ns;   
  constant tTDOH  : time := 12 ns; 

end IURTTimPar;
-------------------------------------------------------------------------------
-- File name : iurt_gen_beh.vhd
-- Title : IURTGeneric (architecture Behavior)
-- project : SPARC 
-- Library : IURT_LIB
-- Author(s) : Maxime ROCCA, Jiri GAISLER
-- Purpose : definition of architecture Behavior for IURTGeneric. It is a beha-
--           -vioral description of the IURT at the highest level.
-- notes : The entity IURTGeneric is defined in the file iurt_gen_ent.vhd.
-- 	
-------------------------------------------------------------------------------
-- Modification history :
-------------------------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
-------------------------------------------------------------------------------
-- v 1.0        |  MR    | 94-03-04     | first version
-- Compliant with the the IURT Device Specification, issue 4++ (i.e certain
-- features implemented in this version of the IU-RT model will only appear in
-- the next issue of the IU-RT Device Specification), except for coprocessor
-- interface.
--.............................................................................
-- v 1.1        |  MR    | 94-05-03     | 2nd version
-- + IURT model is made sensitive to CCCV and CHOLD_N
-- + modif. condition for parity bit checking
-- + bug fix for memory exception (MEXC_N)
-- + bug fix about XHOLD on annulling FP branch
-- + bug fix on ASI generation for load/store instructions in alternate space.
-- + bug fix on return address for trap in particular case.
-- + bug fix for cache miss on branching instruction.
-- + bug fix for memory exception in case of STD or LDD.
-- + modif. definition of IMPAR
-- + change name of tap controller
-- + modelling of buffers slightly modified.
-- + modification concerning parity bit checking
--.............................................................................
-- v 1.2        |  MR    | 94-05-27     | 3rd version
-- + modification of timing checkers
--.............................................................................
-- v 1.3        |  RC    | 95-12-11     | 4th version
-- + modification of the instruction pipeline in order to handle correctly 
--   JMPL and RETT instructions and the address generation in case of CALL
-- v 1.4        |  JG    | 96-03-04     | 5th version
-- + bug fix for memory exception in second data cycle for STD
-- + bug fix for trap handling in LD and LDD
-- v 1.5        |  JG    | 96-09-24     | 6th version
-- + bug fix to supress false warnings
-- + bug fix for INULL geneation and LD/ST hardware interlock
-------------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
-- Copyright ESA/ESTEC
-------------------------------------------------------------------------------
---------|---------|---------|---------|---------|---------|---------|--------|

library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdRtl.all;
use MMS.StdIoImp.all;
use MMS.StdTiming.all;
library SPARC_LIB;
use SPARC_LIB.SparcPck.all;
use SPARC_LIB.TAPCompPck.all;


architecture vhdl_behavioral of IURTGeneric is

  -- constant for modelling
  constant TRI_STATE32 : std_logic_vector(31 downto 0)
                         := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

  -- Pipeline registers:
  --   ID: Instruction Decode stage
  --   EX: EXecute stage
  --   WR: WRite stage
  signal ID, EX, WR : Instruction;
  
  -- Intermediary signals for hold signals:                                 
  -- SIGNALlat = output of a latch (transparent clock high) with signal
  --             SIGNAL as input to the latch.
  -- HOLDsig_N: all hold signals are ANDed together and generate HOLDsig_N.
  signal HOLDsig_N   : std_logic;
  signal FHOLD_Nlat  : std_logic;
  signal CHOLD_Nlat  : std_logic;
  signal BHOLD_Nlat  : std_logic;
  signal MHOLDA_Nlat : std_logic;
  signal MHOLDB_Nlat : std_logic;
  signal FCCVlat     : std_logic;
  signal CCCVlat     : std_logic;
    
  -- Signals inside model corresponding to output or bidirectional port signals.
  -- A signal SIGin corresponds to the output port signal SIG.
  signal Ain      : std_logic_vector(31 downto 0);
  signal APARin   : std_logic;
  signal ASIin    : std_logic_vector(7 downto 0);
  signal Din      : std_logic_vector(31 downto 0);
  signal DPARin   : std_logic;
  signal DXFERin  : std_logic;
  signal INULLin  : std_logic;
  signal LDSTOin  : std_logic;
  signal LOCKin   : std_logic;
  signal RDin     : std_logic;
  signal SIZEin   : std_logic_vector(1 downto 0);
  signal ASPARin  : std_logic;
  signal WE_Nin   : std_logic;
  signal WRTin    : std_logic;
  signal IMPARin  : std_logic;
  signal FINS1in  : std_logic;
  signal FINS2in  : std_logic;
  signal FLUSHin  : std_logic;
  signal FXACKin  : std_logic;
  signal INSTin   : std_logic;
  signal IFPARin  : std_logic;
  signal INTACKin : std_logic;
  signal ERROR_Nin   : std_logic;
  signal HWERROR_Nin : std_logic;
  signal MCERR_Nin   : std_logic;
  
  -- Signals used for the IO buffers modelling
  signal AOE_Ndel : std_logic; 
  signal DOE_Ndel : std_logic; 
  signal COE_Ndel : std_logic;
  signal TOE_Ndel : std_logic; 
  signal HALTsampled : std_logic;
  signal DTHCsig  : std_logic;
  signal ATHCsig  : std_logic;
  signal CTHCsig  : std_logic;
  signal ACTHCsig : std_logic;
  signal THCsig   : std_logic;

  -- Specific signals for inter-process communication used for
  -- timing violation checking.
  signal CheckTimBidir     : boolean := FALSE; -- Checking performed if TRUE
  signal CheckTimBidir_1_i : boolean := FALSE;
  signal CheckTimBidir_1   : boolean := FALSE; -- Checking performed if TRUE
  signal CheckTimBidir_2_i : boolean := FALSE; 
  signal CheckTimBidir_2   : boolean := FALSE; -- Checking performed if TRUE
  
  signal Chk_MEXC_N_en   : boolean;
  signal Chk_BHOLD_N_en  : boolean;
  signal Chk_MHOLDA_N_en : boolean;
  signal Chk_MHOLDB_N_en : boolean;
  signal Chk_FHOLD_N_en  : boolean;
  signal Chk_FCC_en      : boolean;
  signal Chk_MDS_N_en    : boolean;
  signal Chk_FCCV_en     : boolean;
  signal Chk_FEXC_N_en   : boolean;
  signal Chk_FIPAR_en    : boolean;
  signal Chk_FP_N_en     : boolean;
  
    signal Buf1IsValid_Spy : boolean;     -- Flag for validity of buffer 1.
    signal Buf2IsValid_Spy : boolean;     -- Flag for validity of buffer 2.
    signal IOPcase_Spy : boolean; -- set to true if IOP to be scheduled.
  
    signal WR1x, wr2x, wr3x : Instruction;
    signal CurrentAddrx : std_logic_vector(31 downto 0);
  -- Configuration of components
--  for all : TAP_iufpu use entity SPARC_LIB.tap_iufpu(vhdl_behavioral);
     
begin

  IUmodel: process
  
    ------ Declaration zone for process IUmodel ------
    variable PowerUP : boolean := TRUE; -- Start-up flag for initialization.
    variable StartUp : boolean := TRUE; -- Another flag for start-up.
      
    variable Mode : ModeType := RESET_MODE; -- State (or mode) of the 
                                            -- processor when powered up.

    variable TrapMode : TrapModeType := NOTRAP; -- Flag used for pipeline
                                                -- progression.
    
    -- State registers declaration
    variable PSR : std_logic_vector(31 downto 0) :=
	"00000000000000000000000000000000"; -- Processor State Register.
      alias impl : std_logic_vector(3 downto 0) is PSR(31 downto 28);
      alias ver  : std_logic_vector(3 downto 0) is PSR(27 downto 24);
      alias icc  : std_logic_vector(3 downto 0) is PSR(23 downto 20);
      alias Reserved_PSR : std_logic_vector(5 downto 0) is PSR(19 downto 14);
      alias EC   : std_logic is PSR(13);
      alias EF   : std_logic is PSR(12);
      alias PIL  : std_logic_vector(3 downto 0) is PSR(11 downto  8);
      alias S    : std_logic is PSR(7);
      alias PS   : std_logic is PSR(6);
      alias ET   : std_logic is PSR(5);
      alias CWP  : std_logic_vector(4 downto 0) is PSR(4 downto 0);
      
    variable TBR : std_logic_vector(31 downto 0) :=
	"00000000000000000000000000000000"; -- Trap Base Register.
      alias TBA : std_logic_vector(19 downto 0) is TBR(31 downto 12);
      alias tt  : std_logic_vector( 7 downto 0) is TBR(11 downto  4);
      -- bit 3 through 0 of TBR are kept to 0
      
    variable WIM : std_logic_vector(31 downto 0); -- Window Invalid Mask Reg.
    variable   Y : std_logic_vector(31 downto 0); -- Y Register.
    
    -- Register file: 8 global registers + 16*NWINDOWS windowed registers.
    variable RegFile: RegisterFile(16*NWINDOWS+7 downto 0);
    
    -- Address registers (related to Program Counters)
                   -- Current  Address.
    variable SA1CurrentAddr : std_logic_vector(31 downto 0);
    variable CurrentAddr : std_logic_vector(31 downto 0);
                   -- Previous  Address.
    variable PrevAddr : std_logic_vector(31 downto 0);
                   -- Previous to previous Address.
    variable pPrevAddr : std_logic_vector(31 downto 0);
                   -- Save registers for store or load or loadstore
    variable SaveCurrentAddr : std_logic_vector(31 downto 0);
    variable SavePrevAddr : std_logic_vector(31 downto 0);
        
    -- Pipeline buffer declaration + convenient temp. variable
    variable nID : Instruction; -- next Instruction Decode: temp. variable.
    variable nIDisValid  : boolean; -- Flag for validity of nID.
    variable InstBuffer1 : Instruction; -- Instruction Buffer 1.
    variable Buf1IsValid : boolean;     -- Flag for validity of buffer 1.
    variable InstBuffer2 : Instruction; -- Instruction Buffer 2.
    variable Buf2IsValid : boolean;     -- Flag for validity of buffer 2.
    variable IOPcase : boolean; -- set to true if IOP to be scheduled.
    variable nIDTemp : Instruction; -- Temp. variable for nID
    
    -- WR1 and WR2 are fictitious pipeline stages.
    -- WR1: "stage" just after WR stage
    -- WR2: "stage" just after WR1 stage
    -- WR3: "stage" just after WR2 stage
    variable WR1 : Instruction;
    variable WR2 : Instruction;