iurt_lib.vhd

ERC32 经典的sparc v7 cpu

-------------------------------------------------------------------------------
-- File name : iurt_gen_ent.vhd
-- Title : IURTGeneric (entity)
-- project : SPARC 
-- Library : IURTLIB
-- Author(s) : Maxime ROCCA
-- Purpose :  definition of entity IURTGeneric
-- notes :   
-- 	
-------------------------------------------------------------------------------
-- Modification history :
-------------------------------------------------------------------------------
-- Version No : | Author | Mod. Date : | Changes made :
-------------------------------------------------------------------------------
-- v 1.0        |  MR    | 94-03-04    | first version
-- Compliant with the IU-RT Device Specification, issue 4.
--.............................................................................
-- v 1.1        |  MR    | 94-05-27    | 2nd version
-- + modify timing checkers
-------------------------------------------------------------------------------
-- Copyright MATRA MARCONI SPACE FRANCE
 
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Library General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
 
--  This library is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
--  Library General Public License for more details.
 
--  You should have received a copy of the GNU Library General Public
--  License along with this library; if not, write to the Free
--  Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 
-------------------------------------------------------------------------------
---------|---------|---------|---------|---------|---------|---------|--------|

library IEEE;
use IEEE.Std_Logic_1164.all;
library MMS;
use MMS.StdIoImp.all;
use MMS.StdSim.all;
use MMS.StdTiming.all;


entity IURTGeneric is
  generic( -- Fake default timing values.
     tCY   : time := 50 ns; -- Clock cycle
     tCHL  : time := 22 ns; -- Clock high and low
     tAD   : time := 8 ns; -- A,ASI,SIZE,RD,WRT,WE_N,LOCK,LDSTO output delay 
     tAH   : time := 7 ns; -- A,ASI,SIZE,RD,WRT,WE_N,LOCK,LDSTO output valid
     tDOD  : time := 8 ns; -- D output delay
     tDOH  : time := 7 ns; -- D output valid
     tDIS  : time := 5 ns; -- D input setup
     tDIH  : time := 1 ns; -- D input hold
     tMES  : time := 5 ns; -- MEXC_N input setup
     tMEH  : time := 1 ns; -- MEXC_N input hold
     tHS   : time := 5 ns; -- BHOLD_N,MHOLDA_N,MHOLDB_N,FHOLD,CHOLD input setup
     tHH   : time := 1 ns; -- BHOLD_N,MHOLDA_N,MHOLDB_N,FHOLD,CHOLD input hold
     tHOD  : time := 8 ns; -- XHOLD_N to address/control output delay
     tHOH  : time := 8 ns; -- XHOLD_N to address/control output valid
     tOE   : time := 8 ns; -- AOE_N, COE_N, DOE_N to output enable delay
     tOD   : time := 8 ns; -- AOE_N, COE_N, DOE_N to output disable delay
     tTOE  : time := 8 ns; -- TOE_N to output enable delay
     tTOD  : time := 8 ns; -- TOE_N to output disable delay
     tSSD  : time := 8 ns; -- INST, FXACK, CXACK, INTACK output delay
     tSSH  : time := 7 ns; -- INST, FXACK, CXACK, INTACK output valid
     tRS   : time := 5 ns; -- RESET_N input setup
     tRH   : time := 1 ns; -- RESET_N input hold
     tFD   : time := 8 ns; -- FINS, CINS output delay
     tFH   : time := 7 ns; -- FINS, CINS output valid
     tFIS  : time := 5 ns; -- FCC, CCC input setup
     tFIH  : time := 1 ns; -- FCC, CCC input hold
     tDXD  : time := 8 ns; -- DXFER output delay
     tDXH  : time := 7 ns; -- DXFER output valid
     tHDXD : time := 8 ns; -- XHOLD_N asserted to DXFER output delay
     tHDXH : time := 7 ns; -- XHOLD_N asserted to DXFER output valid
     tNUD  : time := 8 ns; -- INULL output delay
     tNUH  : time := 7 ns; -- INULL output valid
     tMDS  : time := 5 ns; -- MDS_N input setup
     tMDH  : time := 1 ns; -- MDS_N input hold
     tFLS  : time := 8 ns; -- FLUSH output delay
     tFLH  : time := 7 ns; -- FLUSH output valid
     tCCVS : time := 5 ns; -- FCCV, CCCV input setup
     tCCVH : time := 1 ns; -- FCCV, CCCV input hold
     tXES  : time := 5 ns; -- FEXC_N, CEXC_N input setup
     tXEH  : time := 1 ns; -- FEXC_N, CEXC_N input hold
     tMAD  : time := 8 ns; -- MAO asserted to address/control output delay
     tMAH  : time := 8 ns; -- MAO asserted to address/control output valid
     tETD  : time := 8 ns; -- HWERROR_N output delay
     tETH  : time := 7 ns; -- HWERROR_N output valid
     tXAPD : time := 8 ns; -- APAR & ASPAR output delay
     tXAPH : time := 7 ns; -- APAR & ASPAR output valid
     tDPOD : time := 8 ns; -- DPAR output delay
     tDPOH : time := 7 ns; -- DPAR output valid
     tDPIS : time := 5 ns; -- DPAR input setup
     tDPIH : time := 1 ns; -- DPAR input hold
     tIFPD : time := 8 ns; -- IFPAR output delay
     tIFPH : time := 7 ns; -- IFPAR output valid
     tFIPS : time := 8 ns; -- FIPAR output delay
     tFIPH : time := 7 ns; -- FIPAR output valid
     tIMPD : time := 8 ns; -- IMPAR output delay
     tIMPH : time := 7 ns; -- IMPAR output valid
     tMCED : time := 8 ns; -- MCERR_N output delay
     tMCEV : time := 7 ns; -- MCERR_N output valid
     tSTATS : time := 5 ns; -- N601MODE_N, FLOW_N, CMODE_N, FP_N input setup
     tHAS  : time := 5 ns; -- HALT_N input setup
     tHAH  : time := 1 ns; -- HALT_N input hold
     tHAE  : time := 8 ns; -- HALT_N asserted to output enable delay
     tHAD  : time := 8 ns; -- HALT_N asserted to output disable delay
     
     tTCY  : time := 50 ns; -- TCLK Clock Cycle
     tTMS  : time := 5 ns; -- TMS setup
     tTMH  : time := 1 ns; -- TMS hold
     tTDIS : time := 5 ns; -- TDI setup
     tTDIH : time := 1 ns; -- TDI hold
     tTRS  : time := 5 ns; -- TRST_N setup
     tTRH  : time := 1 ns; -- TRST_N hold
     tTDOD : time := 8 ns; -- TDO output delay
     tTDOH : time := 7 ns  -- TDO output valid
  );
  
  port(
    -- Note: signals which are functionally output signals but are actually
    -- inout signals because of the Master/Checker mode have an "*" in the 
    -- comments defining their function.
    
    CLK   : in std_logic; -- clock signal
    
    --  Memory Subsystems Interface Signals  
    A        : inout std_logic_vector(31 downto 0); --* Address bus
    APAR     : inout std_logic; --* Address bus Parity
    AOE_N    : in    std_logic; -- Address Output Enable
    ASI      : inout std_logic_vector(7 downto 0); --* Address Space Identifier
    ASPAR    : inout std_logic; --* ASI & SIZE Parity
    BHOLD_N  : in    std_logic; -- Bus Hold
    COE_N    : in    std_logic; -- Control Output Enable
    D        : inout std_logic_vector(31 downto 0); -- Data Bus
    DPAR     : inout std_logic; -- Data Bus Parity
    DOE_N    : in    std_logic; -- Data Output Enable
    DXFER    : inout std_logic; --* Data Transfer
    IFT_N    : in    std_logic; -- Instruction Cache Flush Trap
    INULL    : inout std_logic; --* Integer Unit Nullify Cycle
    LDSTO    : inout std_logic; --* Atomic Load-Store
    LOCK     : inout std_logic; --* Bus Lock
    MAO      : in    std_logic; -- Memory Address Output
    MDS_N    : in    std_logic; -- Memory Data Strobe
    MEXC_N   : in    std_logic; -- Memory Exception
    MHOLDA_N : in    std_logic; -- Memory Hold A
    MHOLDB_N : in    std_logic; -- Memory Hold B
    RD       : inout std_logic; --* Read Access
    SIZE     : inout std_logic_vector(1 downto 0); --* Bus Transaction Size
    WE_N     : inout std_logic; --* Write Enable
    WRT      : inout std_logic; --* Advanced Write
    IMPAR    : inout std_logic; --* IU to MEC Control Parity
    
    -- Interrupt and Control Signals
    ERROR_N    : out std_logic; -- Error State
    HWERROR_N  : out std_logic; -- Hardware error detected
    FLOW_N     : in  std_logic; -- Enable flow control
    MCERR_N    : out std_logic; -- Comparison error
    N601MODE_N : in  std_logic; -- Normal 601Mode Operation
    CMODE_N    : in  std_logic; -- Checker mode
    FPSYN      : in  std_logic; -- Floating-Point Synomym Mode
    INTACK     : inout std_logic; --* Interrupt Acknowledge
    IRL        : in  std_logic_vector(3 downto 0); -- Interrupt Request Level
    RESET_N    : in  std_logic; -- Integer Unit Reset
    TOE_N      : in  std_logic; -- Test Mode Output Enable
    HALT_N     : in  std_logic; -- Halt
    
    -- Floating Point / Coprocessor Interfaces
    FCC     : in    std_logic_vector( 1 downto 0); -- FP Condition Codes
    FCCV    : in    std_logic; -- Floating-Point Condition Codes Valid
    FEXC_N  : in    std_logic; -- Floating-Point Exception
    FHOLD_N : in    std_logic; -- Floating-Point Hold
    FIPAR   : in    std_logic; -- FPU to IU Control Parity
    FINS1   : inout std_logic; --* Floating-Point Instruction in Buffer 1
    FINS2   : inout std_logic; --* Floating-Point Instruction in Buffer 2
    FLUSH   : inout std_logic; --* Floating-Point/Coproc. Instruction Flush
    FP_N    : in    std_logic; -- Floating-Point Unit Present
    FXACK   : inout std_logic; --* Floating-Point Exception Acknowledge
    INST    : inout std_logic; --* Instruction Fetch
    IFPAR   : inout std_logic; --* IU to FPU Control Parity
    CCC     : in    std_logic_vector( 1 downto 0); -- Coproc. Condition Codes
    CCCV    : in    std_logic; -- Coprocessor Condition Codes Valid
    CEXC_N  : in    std_logic; -- Coprocessor Exception
    CHOLD_N : in    std_logic; -- Coprocessor Hold
    CINS1   : inout std_logic; --* Coprocessor Instruction in Buffer 1
    CINS2   : inout std_logic; --* Coprocessor Instruction in Buffer 2
    CP_N    : in    std_logic; -- Coprocessor Unit Present
    CXACK   : inout std_logic; --* Coprocessor Exception Acknowledge

    -- TAP signals
    TCLK      : in  std_logic; -- Test Clock
    TRST_N    : in  std_logic; -- Test Reset
    TMS       : in  std_logic; -- Test Mode Select
    TDI       : in  std_logic; -- Test Data Input
    TDO       : out std_logic  -- Test Data Output
  );
begin
  --  PUT HERE SOME TIMING CHECKERS: SETUP & HOLD TIME + PULSE WIDTH CHECKERS.
  
  SigRESET_N  : SetupHoldCheck(RESET_N, CLK, EDGE => RISING,
                               SETUP => tRS,  HOLD => tRH, 
                               PATH => "RESET_N", 
                               DelayedData => RESET_N'Delayed(abs(tRH)));
    
  SigN601MODE_N  : SetupHoldCheck(N601MODE_N, CLK, EDGE => RISING,
                                  SETUP => tSTATS,  HOLD => 0 ns, 
                                  PATH => "N601MODE_N", 
                                  DelayedData => N601MODE_N'Delayed(0 ns));
  
  SigFLOW_N   : SetupHoldCheck(FLOW_N, CLK, EDGE => RISING,
                               SETUP => tSTATS,  HOLD => 0 ns, 
                               PATH => "FLOW_N", 
                               DelayedData => FLOW_N'Delayed(0 ns));
  
  SigCMODE_N  : SetupHoldCheck(CMODE_N, CLK, EDGE => RISING,
                               SETUP => tSTATS,  HOLD => 0 ns, 
                               PATH => "CMODE_N", 
                               DelayedData => CMODE_N'Delayed(0 ns));
                               
  SigHALT_N   : SetupHoldCheck(HALT_N, CLK, EDGE => FALLING,
                               SETUP => tHAS,  HOLD => tHAH, 
                               PATH => "HALT_N", 
                               DelayedData => HALT_N'Delayed(abs(tHAH)));
      
  SigTMS     : SetupHoldCheck(TMS, TCLK, EDGE => RISING,
                              SETUP => tTMS,  HOLD => tTMH, 
                              PATH => "TMS", 
                              DelayedData => TMS'Delayed(abs(tTMH)));
                                 
  SigTDI     : SetupHoldCheck(TDI, TCLK, EDGE => RISING,
                              SETUP => tTDIS,  HOLD => tTDIH, 
                              PATH => "TDI", 
                              DelayedData => TDI'Delayed(abs(tTDIH)));
                                 
  SigTRST_N  : SetupHoldCheck(TRST_N, TCLK, EDGE => RISING,
                              SETUP => tTRS,  HOLD => tTRH, 
                              PATH => "TRST_N", 
                              DelayedData => TRST_N'Delayed(abs(tTRH)));
    
  
  CLKHigh : PulseCheck(CLK, LEVEL => '1', WIDTH => tCHL, 
                       SENSE => MINIMUM, PATH => "CLK");
                                
  CLKlow  : PulseCheck(CLK, LEVEL => '0', WIDTH => tCHL, 
                       SENSE => MINIMUM, PATH => "CLK");
    
  ---
  CLKCycle : process    -- Passive process.
    variable DeltaT   : time := 0 ns;
    variable LastEdge : time := -1 sec;
  begin
    if not(CHECK_ON) then
      wait; -- the process dies here....
    end if;
    
    wait on CLK until rising_edge(CLK);
    
    DeltaT   := now - LastEdge;
    LastEdge := now;
    
    assert (DeltaT >= tCY)
          report "Clock cycle violation: minimal value is " &
                 ToString(tCY) & "; value observed: " &
                 ToString(DeltaT) & "."
          severity warning;
    
  end process CLKCycle; 

  ----
  RESET_Nwidth : process    -- Passive process.
    constant MIN_NB_RESET_CYCLES : natural := 10;
    variable CountNbResetCycle : natural := 0;
  begin
    if not(CHECK_ON) then
      wait; -- the process dies here....
    end if;
    
    wait on CLK until rising_edge(CLK);
    
    if RESET_N = '1' then
      if CountNbResetCycle /= 0 and CountNbResetCycle < MIN_NB_RESET_CYCLES then
        assert FALSE
          report "Pulse width violation for RESET_N: should stay low for at " & 
                 "least " & ToString(MIN_NB_RESET_CYCLES) & 
                 " rising clock edges!"
          severity warning;
      end if;
      CountNbResetCycle := 0;
    elsif RESET_N = '0' then
      CountNbResetCycle := CountNbResetCycle + 1;
    end if;
    
  end process RESET_Nwidth; 
  
end IURTGeneric;
-------------------------------------------------------------
-- File containing timing values for the IURT VHDL model.
-- 
-- ALL THE TIMING PARAMETERS are given at 125 degrees C,  
-- 4.5 Volts and in worst case process conditions.
-- WARNING: minimal values for output signal propagation 
-- delay in data sheets are usually given in best conditions,  
-- i.e -55 Celsius, 5.5 Volts and best case process conditions.
-- They must be re-calculated for worst case conditions.
-------------------------------------------------------------