adc0809eda程序.txt

本程序是用VHDL语言写的

--------------------------------------------------------------------
library IEEE;                   顶层文件
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IDT7132ZH is
port(clk,clr,eoc:in std_logic;
               m,clkk:in std_logic;
               d:in std_logic_vector(7 downto 0);
    ale,start,oe:out std_logic;
        en,wr,rd:out std_logic;
              p0:out std_logic_vector(7 downto 0);
              dz:out std_logic_vector(10 downto 0));
end IDT7132ZH;

architecture Behavioral of IDT7132ZH is
		COMPONENT idt7132ad
	PORT(
		D : IN std_logic_vector(7 downto 0);
		CLK : IN std_logic;
		clkk : IN std_logic;
		clr : IN std_logic;
		EOC : IN std_logic;          
		ALE : OUT std_logic;
		START : OUT std_logic;
		OE : OUT std_logic;
		clx : OUT std_logic;
		Q : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
  	COMPONENT idt7132b
	PORT(
		DATA : IN std_logic_vector(7 downto 0);
		M : IN std_logic;
		gg : IN std_logic;
		CLR : IN std_logic;          
		T : OUT std_logic;
		TW : OUT std_logic;
		DZA : OUT std_logic_vector(10 downto 0);
		SJ : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
	COMPONENT idt7132a
	PORT(
		CLK : IN std_logic;
		CLR : IN std_logic;
		M : IN std_logic;
		TW : IN std_logic;
		CLKK : IN std_logic;
		DZA : IN std_logic_vector(10 downto 0);
		SJ : IN std_logic_vector(7 downto 0);          
		P0 : OUT std_logic_vector(7 downto 0);
		DZ : OUT std_logic_vector(10 downto 0);
		EN : OUT std_logic;
		WR : OUT std_logic;
		RD : OUT std_logic
		);
	END COMPONENT;
	signal data1:std_logic_vector(7 downto 0);
	signal clx1:std_logic;
	signal t1,tw1:std_logic;
	signal dza1:std_logic_vector(10 downto 0);
	signal sj1:std_logic_vector(7 downto 0);
begin
 	Inst_idt7132ad: idt7132ad PORT MAP(
		D => d,
		CLK =>clk ,
		clkk =>clkk ,
		clr =>clr ,
		EOC =>eoc ,
		ALE => ale,
		START =>start ,
		OE =>oe ,
		clx =>clx1 ,
		Q =>data1 
	);

 
	Inst_idt7132b: idt7132b PORT MAP(
		DATA =>data1 ,
		M => m,
		gg => clx1,
		CLR =>clr ,
		T =>t1 ,
		TW => tw1,
		DZA => dza1,
		SJ => sj1
	);
 	Inst_idt7132a: idt7132a PORT MAP(
		CLK => clk,
		CLR => clr,
		M =>m ,
		TW =>tw1 ,
		CLKK =>t1 ,
		DZA =>dza1 ,
		SJ =>sj1 ,
		P0 => p0,
		DZ => dz,
		EN => en,
		WR => wr,
		RD => rd
	);




end Behavioral;


+++++++++++++++++++++++++++++++++++++++++++++++++++AD转换模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IDT7132AD is
    Port ( D : in std_logic_vector(7 downto 0);
		 CLK,clkk:  in std_logic;
		 clr:in std_logic;
           EOC : in std_logic;
  ALE,START,OE : out std_logic;
		 clx:out std_logic;
           Q : out std_logic_vector(7 downto 0));
end IDT7132AD;

architecture Behavioral of IDT7132AD is
type states is(st0,st1,st2,st3,st4,st5,st6);
signal ur1,ur2:states;
signal regl:std_logic_vector(7 downto 0);
signal lock:std_logic;
signal qq:std_logic;
begin
process(ur1,eoc,QQ,clr)
begin	
if clr='1' then  start<='0';oe<='0';lock<='0';ur2<=st0;
elsif QQ'event and QQ='1'then 
case ur1 is
when st0 =>ale<='0';start<='0';oe<='0';lock<='0';
     ur2<=st1;
when st1 =>ale<='1';start<='0';oe<='0';lock<='0';
     ur2<=st2;
when st2=>ale<='0';start<='1';oe<='0';lock<='0';
     ur2<=st3;
when st3=>ale<='0';start<='0';oe<='0';lock<='0';
     if(eoc='1')then ur2<=st3;
	else ur2<=st4;
	end if;
when st4=> ale<='0';start<='0';oe<='0';lock<='0';
     if (eoc='0')then ur2<=st4;
	else ur2<=st5;
	end if;
when st5=>ale<='0';start<='0';oe<='1';lock<='0';
     ur2<=st6;
when st6=>ale<='0';start<='0';oe<='1';lock<='1';
     ur2<=st0;
when others=>ale<='0';start<='0';oe<='0';lock<='0';
     ur2<=st0;
end case;
end if;
end process;
process(QQ)
begin
 if QQ'event and QQ='1'then 
     ur1<=ur2;
	end if;
	end process;
process(lock)
begin
if lock'event and lock='1'then  regl<=d;
end if;
end process;
process(clk,CLKK)
begin
if clk'event and clk='1' then 
qq<=clkk;
end if;
end process;
q<=regl;
clx<=not lock;
end Behavioral;



+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;   数据地址模块。
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IDT7132B is
    Port ( DATA: in std_logic_vector(7 downto 0);
           M : in std_logic;
		 gg: in std_logic;
           CLR : in std_logic;
		    T: out std_logic;
            TW : out std_logic;
           DZA : out std_logic_vector(10 downto 0);
           SJ : out std_logic_vector(7 downto 0));
end IDT7132B;

architecture Behavioral of IDT7132B is
signal Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal t1:std_logic;
begin
process(gg,clr)
begin
if clr='1'then q<="0000";
elsif gg'event and gg='1' then  if m='1'then if q="1010"then q<="0000";
else q<=q+1;
end if;
end if;
end if;
end process;
process(gg,q,clr)
begin
if clr='1'then tw<='0';DZA<="00000000000";SJ<=(OTHERS=>'0');
elsif gg'event and gg='1'then if m='1'then 	 
case q is
when "0000"=>DZA<="00000000000";SJ<=DATA;
when "0001"=>DZA<="00000000001";SJ<=DATA;
when "0010"=>DZA<="00000000010";SJ<=DATA;
when "0011"=>DZA<="00000000011";SJ<=DATA;
when "0100"=>DZA<="00000000100";SJ<=DATA;
when "0101"=>DZA<="00000000101";SJ<=DATA;
when "0110"=>DZA<="00000000110";SJ<=DATA;
when "0111"=>DZA<="00000000111";SJ<=DATA;
when "1000"=>DZA<="00000001000";SJ<=DATA;
when "1001"=>DZA<="00000001000";SJ<=DATA;tw<='1';
when others=>null;
end case;
end if;
end if;
end process;
t<=not gg;
end Behavioral;

-------------------------------------------数据地址发送模块。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 ENTITY IDT7132A IS
PORT(CLK,CLR,M,TW,CLKK:IN STD_LOGIC;
              DZA:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
		     SJ:IN STD_LOGIC_VECTOR(7 DOWNTO 0 );
            P0:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
            DZ:OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
         EN,WR,RD:OUT STD_LOGIC);
END;
ARCHITECTURE ONE OF IDT7132A IS
SIGNAL W,D,S,EN1:STD_LOGIC;
SIGNAL DZZ:STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL P00:STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE DAO IS(ST0,ST1,ST2,ST3,ST4);
SIGNAL  UR1,UR2:DAO;
SIGNAL  Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,CLR,M)
BEGIN
IF CLR='1'THEN UR2<=ST0;W<='1';RD<='0';WR<='0';D<='0';S<='0';
ELSIF CLK'EVENT AND CLK='1'THEN
CASE UR1 IS
WHEN ST0=>IF M='1'THEN UR2<=ST1;ELSE UR2<=ST0;END IF;
WHEN ST1=>IF W='1'THEN UR2<=ST2;ELSE UR2<=ST1;END IF;
WHEN ST2=>UR2<=ST3;D<='1';
WHEN ST3=>RD<='1';WR<='0';UR2<=ST4;
WHEN ST4=>W<='0';UR2<=ST0;S<='1';
WHEN OTHERS=>UR2<=ST0;
END CASE;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'THEN UR1<=UR2;
END IF;
END PROCESS;
PROCESS(S,CLR,EN1)
BEGIN
IF CLR='1'THEN EN1<='0';
ELSIF S'EVENT AND S='1'THEN
EN1<='1';
END IF;
END PROCESS;
PROCESS(CLK,EN1,CLR)
BEGIN
IF CLR='1'THEN Q<="0000";EN<='0';
ELSIF CLK'EVENT AND CLK='1'THEN IF( Q="1000" AND TW='1')THEN EN<=EN1;Q<="0000";
ELSE Q<=Q+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKK,DZA,SJ)
BEGIN
IF CLKK'EVENT AND CLKK='1'THEN DZZ<=DZA;P00<=SJ;
END IF;
END PROCESS;
DZ<=DZZ WHEN D ='1'ELSE
    "ZZZZZZZZZZZ";
P0<=P00 WHEN S ='1'ELSE
    "ZZZZZZZZ";
END;
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