双口ram已调程序.txt

本程序是用VHDL语言写的

说明:在使用此程序时注意不要在最前最后一个数据地址单元存放数据地址，否则可能丢失。
       使用时只需要将数据地址分别放入数据地址单元便可。
此模块为验证模块，DAZ,SJ:分别存放地址数据。




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LIBRARY IEEE;主模块负责把数据,地址发送到双口RAM；
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 ENTITY IDT7132A IS
PORT(CLK,CLR,M,TW,CLKK:IN STD_LOGIC; M:由单片机控制，TW：用于控制EN信号。关闭双口RAM
              DZA:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
		     SJ:IN STD_LOGIC_VECTOR(7 DOWNTO 0 );
            P0:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
            DZ:OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
         EN,WR,RD:OUT STD_LOGIC);
END;
ARCHITECTURE ONE OF IDT7132A IS
SIGNAL W,D,S,EN1:STD_LOGIC;
SIGNAL DZZ:STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL P00:STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE DAO IS(ST0,ST1,ST2,ST3,ST4);
SIGNAL  UR1,UR2:DAO;
SIGNAL  Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,CLR,M)
BEGIN
IF CLR='1'THEN UR2<=ST0;W<='1';RD<='0';WR<='0';D<='0';S<='0';
ELSIF CLK'EVENT AND CLK='1'THEN
CASE UR1 IS
WHEN ST0=>IF M='1'THEN UR2<=ST1;ELSE UR2<=ST0;END IF;
WHEN ST1=>IF W='1'THEN UR2<=ST2;ELSE UR2<=ST1;END IF;
WHEN ST2=>UR2<=ST3;D<='1';
WHEN ST3=>RD<='1';WR<='0';UR2<=ST4;
WHEN ST4=>W<='0';UR2<=ST0;S<='1';
WHEN OTHERS=>UR2<=ST0;
END CASE;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1'THEN UR1<=UR2;
END IF;
END PROCESS;
PROCESS(S,CLR,EN1)
BEGIN
IF CLR='1'THEN EN1<='0';
ELSIF S'EVENT AND S='1'THEN
EN1<='1';
END IF;
END PROCESS;
PROCESS(CLK,EN1,CLR)
BEGIN
IF CLR='1'THEN Q<="0000";EN<='0';
ELSIF CLK'EVENT AND CLK='1'THEN IF( Q="1000" AND TW='1')THEN EN<=EN1;Q<="0000";
ELSE Q<=Q+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKK,DZA,SJ)
BEGIN
IF CLKK'EVENT AND CLKK='1'THEN DZZ<=DZA;P00<=SJ;
END IF;
END PROCESS;
DZ<=DZZ WHEN D ='1'ELSE
    "ZZZZZZZZZZZ";
P0<=P00 WHEN S ='1'ELSE
    "ZZZZZZZZ";
END;
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library IEEE;  ;发送数据地址模块。
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IDT7132B is          
    Port ( CLK : in std_logic;
           M : in std_logic;
           CLR : in std_logic;
           T: out std_logic;
           TW : out std_logic;
           DZA : out std_logic_vector(10 downto 0);
           SJ : out std_logic_vector(7 downto 0));
end IDT7132B;

architecture Behavioral of IDT7132B is
signal Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
type  qing is (st0,st1,st2,st3,st4);
signal tt:std_logic;
signal ur1,ur2:qing;
signal w,clm:std_logic;
begin
process(clk,clr,m)
begin
if clr='1'then w<='1';ur2<=st0;tt<='0';clm<='0';
elsif clk'event and clk='1'then 
case ur1 is
when st0=>if m='1'then ur2<=st1;else ur2<=st0;end if;
when st1=>if w='1'then ur2<=st2;else ur2<=st1;end if;
when st2=>clm<=not clm;ur2<=st3;
when st3=>tt<='1';ur2<=st4;
when st4=>if q="1001"then w<='0';tt<='0';ur2<=st1;else ur2<=st2;tt<='0';end if;
when others=>ur2<=st0;
end case;
end if;
end process;
process(clm,clr)
begin
if clr='1'then q<="0000";
elsif clm'event and clm='1'then q<=q+1;
end if;
end process;
process(tt,q,clr)
begin
if clr='1'then tw<='0';DZA<="00000000000";SJ<="00000000";
elsif tt'event and tt='1'then
case q is
when "0000"=>DZA<="00000000000";SJ<="00000000";
when "0001"=>DZA<="00000010010";SJ<="00001000";
when "0010"=>DZA<="00000010011";SJ<="00000111";
when "0011"=>DZA<="00000010100";SJ<="00000110";
when "0100"=>DZA<="00000010101";SJ<="00000101";
when "0101"=>DZA<="00000010110";SJ<="00000100";
when "0110"=>DZA<="00000010111";SJ<="00000011";
when "0111"=>DZA<="00000011000";SJ<="00000010";
when "1000"=>DZA<="00000011001";SJ<="00000001";
when "1001"=>DZA<="00000011001";SJ<="00001000";tw<='1';
when others=>null;
end case;
end if;
end process;
t<=tt;
process(clk)
begin
if clk'event and clk='1'then
ur1<=ur2;
end if;
end process;
end Behavior

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library IEEE;  ;用于连接的连接模块。
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IDT7132D is
    Port ( CLK,CLR,M : in std_logic;
           EN,WR,RD : out std_logic;
           P0 : out std_logic_vector(7 downto 0);
           DZ : out std_logic_vector(10 downto 0));
end IDT7132D;

architecture Behavioral of IDT7132D is
COMPONENT idt7132a
	PORT(
		CLK : IN std_logic;
		CLR : IN std_logic;
		M : IN std_logic;
		TW : IN std_logic;
		CLKK : IN std_logic;
		DZA : IN std_logic_vector(10 downto 0);
		SJ : IN std_logic_vector(7 downto 0);          
		P0 : OUT std_logic_vector(7 downto 0);
		DZ : OUT std_logic_vector(10 downto 0);
		EN : OUT std_logic;
		WR : OUT std_logic;
		RD : OUT std_logic
		);
	END COMPONENT;
 
	COMPONENT idt7132b
	PORT(
		CLK : IN std_logic;
		M : IN std_logic;
		CLR : IN std_logic;          
		T : OUT std_logic;
		TW : OUT std_logic;
		DZA : OUT std_logic_vector(10 downto 0);
		SJ : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
SIGNAL DD: STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL T1,TW1: STD_LOGIC;
SIGNAL SS: STD_LOGIC_VECTOR(7 DOWNTO 0);

begin
Inst_idt7132a: idt7132a PORT MAP(
		CLK => CLK,
		CLR => CLR,
		M => M,
		DZA =>DD ,
		CLKK=>T1,
		TW=>TW1,
		SJ => SS,
		P0 => P0,
		DZ => DZ,
		EN => EN,
		WR => WR,
		RD => RD  );
Inst_idt7132b: idt7132b PORT MAP(
		CLK => CLK,
		M => M,
		CLR =>CLR ,
		T =>T1 ,
		TW => TW1,
		DZA => DD,
		SJ => SS );

end Behavioral;

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