vgavga.syr

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 10-bit up counter                                     : 1
 9-bit up counter                                      : 1
# Registers                                            : 6
 Flip-Flops                                            : 6
# Comparators                                          : 1
 9-bit comparator less                                 : 1
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <vgavga> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vgavga, actual ratio is 1.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 25
 Flip-Flops                                            : 25

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : vgavga.ngr
Top Level Output File Name         : vgavga
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 8

Cell Usage :
# BELS                             : 74
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 17
#      LUT2                        : 2
#      LUT3                        : 2
#      LUT3_L                      : 2
#      LUT4                        : 9
#      LUT4_D                      : 1
#      LUT4_L                      : 1
#      MUXCY                       : 17
#      VCC                         : 1
#      XORCY                       : 17
# FlipFlops/Latches                : 25
#      FD                          : 5
#      FDE                         : 9
#      FDR                         : 11
# Clock Buffers                    : 2
#      BUFG                        : 2
# IO Buffers                       : 8
#      IBUF                        : 2
#      IBUFG                       : 1
#      OBUF                        : 5
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      19  out of   1920     0%  
 Number of Slice Flip Flops:            25  out of   3840     0%  
 Number of 4 input LUTs:                38  out of   3840     0%  
 Number of IOs:                          8
 Number of bonded IOBs:                  8  out of    173     4%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCMs:                         1  out of      4    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-----------------------------+-------+
Clock Signal                       | Clock buffer(FF name)       | Load  |
-----------------------------------+-----------------------------+-------+
clock                              | instance_name/DCM_INST:CLKFX| 25    |
-----------------------------------+-----------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 3.070ns (Maximum Frequency: 325.680MHz)
   Minimum input arrival time before clock: 2.791ns
   Maximum output required time after clock: 8.517ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
  Clock period: 3.070ns (frequency: 325.680MHz)
  Total number of paths / destination ports: 333 / 45
-------------------------------------------------------------------------
Delay:               6.141ns (Levels of Logic = 2)
  Source:            syncgen/CounterX_5 (FF)
  Destination:       syncgen/CounterX_0 (FF)
  Source Clock:      clock rising 0.5X
  Destination Clock: clock rising 0.5X

  Data Path: syncgen/CounterX_5 to syncgen/CounterX_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.720   1.256  syncgen/CounterX_5 (syncgen/CounterX_5)
     LUT4:I0->O            2   0.551   0.903  syncgen/inDisplayArea_mux0000313 (syncgen/inDisplayArea_mux00003_map7)
     LUT4:I3->O           10   0.551   1.134  syncgen/inDisplayArea_mux0000320 (syncgen/CounterXmaxed)
     FDR:R                     1.026          syncgen/CounterX_0
    ----------------------------------------
    Total                      6.141ns (2.848ns logic, 3.293ns route)
                                       (46.4% logic, 53.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clock'
  Total number of paths / destination ports: 4 / 3
-------------------------------------------------------------------------
Offset:              2.791ns (Levels of Logic = 2)
  Source:            key<1> (PAD)
  Destination:       vga_B (FF)
  Destination Clock: clock rising 0.5X

  Data Path: key<1> to vga_B
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   1.216  key_1_IBUF (key_1_IBUF)
     LUT2:I0->O            1   0.551   0.000  vga_B_mux00001 (vga_B_mux0000)
     FD:D                      0.203          vga_B
    ----------------------------------------
    Total                      2.791ns (1.575ns logic, 1.216ns route)
                                       (56.4% logic, 43.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              8.517ns (Levels of Logic = 2)
  Source:            syncgen/vga_VS (FF)
  Destination:       vga_v_sync (PAD)
  Source Clock:      clock rising 0.5X

  Data Path: syncgen/vga_VS to vga_v_sync
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.720   0.801  syncgen/vga_VS (syncgen/vga_VS)
     INV:I->O              1   0.551   0.801  syncgen/vga_v_sync1_INV_0 (vga_v_sync_OBUF)
     OBUF:I->O                 5.644          vga_v_sync_OBUF (vga_v_sync)
    ----------------------------------------
    Total                      8.517ns (6.915ns logic, 1.602ns route)
                                       (81.2% logic, 18.8% route)

=========================================================================
CPU : 5.45 / 5.72 s | Elapsed : 5.00 / 6.00 s
 
--> 

Total memory usage is 138740 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    0 (   0 filtered)