vgavga.syr

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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--> Reading design: vgavga.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "vgavga.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "vgavga"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : vgavga
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Library Search Order               : vgavga.lso
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "my_dcm.v" in library work
Compiling verilog file "hvsync_generator.v" in library work
Module <my_dcm> compiled
Compiling verilog file "vgavga.v" in library work
Module <hvsync_generator> compiled
Module <vgavga> compiled
No errors in compilation
Analysis of file <"vgavga.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <vgavga> in library <work>.

Analyzing hierarchy for module <hvsync_generator> in library <work>.

Analyzing hierarchy for module <my_dcm> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <vgavga>.
WARNING:Xst:852 - "vgavga.v" line 33: Unconnected input port 'RST_IN' of instance 'instance_name' is tied to GND.
Module <vgavga> is correct for synthesis.
 
Analyzing module <hvsync_generator> in library <work>.
Module <hvsync_generator> is correct for synthesis.
 
Analyzing module <my_dcm> in library <work>.
Module <my_dcm> is correct for synthesis.
 
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <my_dcm>.
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <my_dcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <my_dcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "CLKFX_DIVIDE =  4" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "CLKIN_PERIOD =  20.0000000000000000" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "FACTORY_JF =  8080" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <my_dcm>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <my_dcm>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <hvsync_generator>.
    Related source file is "hvsync_generator.v".
    Found 10-bit up counter for signal <CounterX>.
    Found 9-bit up counter for signal <CounterY>.
    Found 1-bit register for signal <inDisplayArea>.
    Found 9-bit comparator less for signal <inDisplayArea$cmp_lt0000> created at line 32.
    Found 1-bit register for signal <vga_HS>.
    Found 1-bit register for signal <vga_VS>.
    Summary:
	inferred   2 Counter(s).
	inferred   3 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <hvsync_generator> synthesized.


Synthesizing Unit <my_dcm>.
    Related source file is "my_dcm.v".
Unit <my_dcm> synthesized.


Synthesizing Unit <vgavga>.
    Related source file is "vgavga.v".
WARNING:Xst:646 - Signal <B> is assigned but never used.
WARNING:Xst:646 - Signal <G> is assigned but never used.
WARNING:Xst:646 - Signal <R> is assigned but never used.
WARNING:Xst:646 - Signal <CounterX<2:0>> is assigned but never used.
WARNING:Xst:646 - Signal <CounterY<2:0>> is assigned but never used.
    Found 1-bit register for signal <vga_B>.
    Found 1-bit register for signal <vga_G>.
    Found 1-bit register for signal <vga_R>.
    Found 1-bit 4-to-1 multiplexer for signal <vga_G$mux0000>.
    Found 1-bit 4-to-1 multiplexer for signal <vga_R$mux0000>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <vgavga> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 2
 10-bit up counter                                     : 1
 9-bit up counter                                      : 1
# Registers                                            : 6
 1-bit register                                        : 6
# Comparators                                          : 1
 9-bit comparator less                                 : 1
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '3s200.nph' in environment E:\Program Files\xp\Xilinx92i.