with_sdram_daq.v

fpga开发pci的verilog

module WITH_SDRAM_DAQ(
       clkin,
       rst,
       ld,ads,lwr,ready,blast,lhold,lholda,lint,la,lwait,ccs,bterm,user_i,user_o,
	   led,
	   dq,sa,ba,cke,cs_n,ras_n,cas_n,we_n,dqm,sdramclk	   
		);
//-------------------------------------------------
input	clkin;
input	rst;
inout	[31:0]	ld;
input	ads,lwr,blast,lhold,lwait,user_o;
input 	[13:0] la;
output 	ready,lholda,lint,bterm,ccs,user_i;
output  [3:0] led;

inout	[31:0]	dq;
output	[10:0]	sa;
output	[1:0]	ba;
output			cke;
output			cs_n;
output			ras_n;
output			cas_n;
output			we_n;
output	[3:0]	dqm; 
output			sdramclk;
//-------------------------------------------------
wire			qd;
wire	[15:0]	r_ram_wab;
wire			r_ram_wdb;
wire			r_ram_wen;
wire			r_req;
wire	[10:0]	r_ram_rab;
wire	[31:0]	r_ram_rdb;
wire			start_read;
wire 			lint;
wire	[31:0]	fifo_in;
wire	[10:0]  rdusedw;
wire	[10:0]  wrusedw;
wire			rdreq;
wire			wr_aclr,rd_aclr;
wire	[31:0] 	fifo_out;      
wire	[13:0]	la;
wire			ready,lholda,ccs;
wire	[7:0] 	ReceiveFlag;
wire	[3:0] 	led;
wire			clkindv2,clkinmp2;

wire	[31:0]	s_ram_wdb;
wire			s_ram_wen;
wire	[2:0]   cmd;
wire			cmdack;
wire	[20:0]  addr;
wire	[31:0]  datain;
wire	[31:0]  dataout;

wire 	[10:0]  sa   ; 
wire 	[1:0]   ba   ; 
wire         	cs_n ;
wire         	cke  ;
wire         	ras_n;
wire         	cas_n;
wire         	we_n ;
wire 	[31:0]  dq   ;  
wire	[3:0]	dqm;
wire			sdramclk;

//-------------------------------------------------
assign led[0] = (ReceiveFlag == 8'h0F);
assign led[1] = s_ram_wen;
assign led[2] = r_req;
assign led[3] = (ReceiveFlag == 8'hF0);
//-------------------------------------------------
reg	clkdv4,clkdv8,clkdv16,clkdv32;
always @(posedge clkindv2 or negedge rst)
	if(!rst)
		clkdv4 <= 0;
	else
		clkdv4 <= ~clkdv4;//10MHz

always @(posedge clkdv4 or negedge rst)
	if(!rst)
		clkdv8 <= 0;
	else
		clkdv8 <= ~clkdv8;//5MHz

always @(posedge clkdv8 or negedge rst)
	if(!rst)
		clkdv16 <= 0;
	else
		clkdv16 <= ~clkdv16;//2.5MHz

always @(posedge clkdv16 or negedge rst)
	if(!rst)
		clkdv32 <= 0;
	else
		clkdv32 <= ~clkdv32;//1.25MHz
//---------------------------------------------------
rec_src source(	
				.rst		(rst),
				.clk		(clkdv4),		
				.qd			(qd),
				.ReceiveFlag(ReceiveFlag)
		       );
	
receiver receiver0(  
				.rst		(rst),	
				.qd			(qd),
				.clk		(clkdv4),
				.r_ram_wdb	(r_ram_wdb),
				.r_ram_wab	(r_ram_wab),
				.r_ram_wen	(r_ram_wen),
				.r_req		(r_req),
				.start_read	(start_read)
				);	

dpram16k_1to512_32 dpram( 
				.data     	(r_ram_wdb),
				.wren     	(r_ram_wen),
				.wraddress	(r_ram_wab),
				.rdaddress	(r_ram_rab),
				.wrclock  	(clkdv4),
				.rdclock  	(clkin),
				.q        	(r_ram_rdb)
				); 

wire	[31:0]	r_ram_rdb_bit_adjust;
assign	r_ram_rdb_bit_adjust[0] = r_ram_rdb[3],
		r_ram_rdb_bit_adjust[1] = r_ram_rdb[2],
		r_ram_rdb_bit_adjust[2] = r_ram_rdb[1],
		r_ram_rdb_bit_adjust[3] = r_ram_rdb[0],
		
		r_ram_rdb_bit_adjust[4] = r_ram_rdb[7],
		r_ram_rdb_bit_adjust[5] = r_ram_rdb[6],
		r_ram_rdb_bit_adjust[6] = r_ram_rdb[5],
		r_ram_rdb_bit_adjust[7] = r_ram_rdb[4],
		
		r_ram_rdb_bit_adjust[8] = r_ram_rdb[11],		
		r_ram_rdb_bit_adjust[9] = r_ram_rdb[10],
		r_ram_rdb_bit_adjust[10] = r_ram_rdb[9],
		r_ram_rdb_bit_adjust[11] = r_ram_rdb[8],
		
		r_ram_rdb_bit_adjust[12] = r_ram_rdb[15],		
		r_ram_rdb_bit_adjust[13] = r_ram_rdb[14],
		r_ram_rdb_bit_adjust[14] = r_ram_rdb[13],
		r_ram_rdb_bit_adjust[15] = r_ram_rdb[12],
		
		r_ram_rdb_bit_adjust[16] = r_ram_rdb[19],		
		r_ram_rdb_bit_adjust[17] = r_ram_rdb[18],
		r_ram_rdb_bit_adjust[18] = r_ram_rdb[17],
		r_ram_rdb_bit_adjust[19] = r_ram_rdb[16],
		
		r_ram_rdb_bit_adjust[20] = r_ram_rdb[23],		
		r_ram_rdb_bit_adjust[21] = r_ram_rdb[22],
		r_ram_rdb_bit_adjust[22] = r_ram_rdb[21],
		r_ram_rdb_bit_adjust[23] = r_ram_rdb[20],
		
		r_ram_rdb_bit_adjust[24] = r_ram_rdb[27],		
		r_ram_rdb_bit_adjust[25] = r_ram_rdb[26],
		r_ram_rdb_bit_adjust[26] = r_ram_rdb[25],
		r_ram_rdb_bit_adjust[27] = r_ram_rdb[24],
		
		r_ram_rdb_bit_adjust[28] = r_ram_rdb[31],		
		r_ram_rdb_bit_adjust[29] = r_ram_rdb[30],
		r_ram_rdb_bit_adjust[30] = r_ram_rdb[29],
		r_ram_rdb_bit_adjust[31] = r_ram_rdb[28];
		
datacnt mydatacnt(	
				.clk		(clkin),
				.rst		(rst),
				.r_ram_rdb	(r_ram_rdb_bit_adjust),	
				.r_ram_rab	(r_ram_rab),	
				.r_req		(r_req),
				
				.s_ram_wdb	(s_ram_wdb),
        		.fifo_wen	(fifo_wen),
                     
		        .cmd      	(cmd      ),
		        .cmdack   	(cmdack   ),
		        .addr     	(addr     ),
		        .datain   	(datain   ),
				.dataout	(dataout),
				
				.start_read	(start_read),
				.interrupt	(lint),
				.rdusedw	(rdusedw),
				.wrusedw	(wrusedw),
				.s_fifo_rst	(s_fifo_rst)
			    );

sdr_sdram mysdr_sdram(
		        .CLK    (clkin),
		        .RESET_N(rst),
		        .ADDR   (addr),
		        .CMD    (cmd),
		        .CMDACK (cmdack),
		        .DATAIN (datain),    
		        .DATAOUT(dataout),
		        .SA     (sa),
		        .BA     (ba),
		        .CS_N   (cs_n),
		        .CKE    (cke),
		        .RAS_N  (ras_n),
		        .CAS_N  (cas_n),
		        .WE_N   (we_n),
		        .DQ     (dq)
		        );
//-------------------------------------------------
assign dqm = 4'd0;
assign sdramclk = clkin;
//---------------------------------------------------
fifo1k_32 fifo(
				.data(s_ram_wdb),
				.wrreq(fifo_wen),
				.rdreq(rdreq),				
				.rdclk(clkin),
				.wrclk(clkin),
				.aclr(!rst),
				.q(fifo_out),
				.rdusedw(rdusedw),
				.wrusedw(wrusedw)
				);

plx_r plx9054(
				.clk(clkin),
				.lrst(rst),
				.ld(ld),
				.ads(ads),
				.lwr(lwr),
				.ready(ready),
				.lwait(lwait),
				.blast(blast),
				.lhold(lhold),
				.lholda(lholda),
				.la(la),
				.ccs(ccs),
				.bterm(bterm),
				.user_i(user_i),
				.user_o(user_o),
				.fifo_out(fifo_out),
				.rdreq(rdreq),
				.ReceiveFlag(ReceiveFlag)
				);
	
pll0 mypll(
			.inclk0(clkin),
			.c0(clkindv2),
			.c1(clkinmp2)
			);
			
endmodule