rec_src.v

fpga开发pci的verilog

module rec_src(
			rst,		
	        clk,		
	        qd,
			ReceiveFlag
	        );
	        
input          rst,clk;
output         qd;
input		   [7:0]	ReceiveFlag;

reg            qd;

reg  [1:0]     count;
reg  [31:0]    vcnt;
reg  [31:0]    hcnt;
reg            blankout;

always @ (posedge clk or negedge rst)
if(!rst)
    vcnt <= 32'b0;
else if((ReceiveFlag == 8'hF0) && (vcnt <='d17440))//'d8192
	vcnt <= vcnt + 1'b1;
else if(ReceiveFlag == 8'h0F)
	vcnt <= 32'b0;
else
	vcnt <= 32'b0;

always @ (posedge clk or negedge rst)
if(!rst)
    blankout <= 1'b0;
else if( vcnt>='d10 && vcnt <'d16416+'d10)//'d7168
    blankout <= 1'b1;
else
    blankout <= 1'b0;
    
always @ (posedge clk or negedge rst)
if(!rst)
	count <= 2'd3;
else if(blankout)
	count <= count - 1'b1;
else
	count <= 2'd3;
	
reg	[2:0]	cnt;
always @ (posedge clk or negedge rst)
if(!rst)
	cnt <= 3'b0;
else if(blankout) begin
	if(count == 'd0)
		cnt <= cnt + 1'b1;
	end
else
	cnt <= 3'b0;
		
wire   [4:0]   number = count + (cnt<<2);
reg	[31:0]	data;              
always @ (posedge clk or negedge rst)
if(!rst) begin
    hcnt[31:24] <= 8'hd1 ;
    hcnt[23:16] <= 8'hcf ;
    hcnt[15:8] <= 8'hfc ;
    hcnt[7:0]  <= 8'ha1 ;
	data <= hcnt;
    end
else if(blankout) begin
	if(number == 'd28) begin//number = 5'b11100, count = 2'b00, cnt = 3'b111;
		hcnt <= data;
   		if(vcnt!='d16394)//'d7178
    		data <= data + 1'b1;
    	end
    end
else begin
    hcnt[31:24] <= 8'hd1 ;
    hcnt[23:16] <= 8'hcf ;
    hcnt[15:8] <= 8'hfc ;
    hcnt[7:0]  <= 8'ha1 ;
    end

always @ (posedge clk or negedge rst)
if(!rst)
    qd <= 1'b0;
else if(blankout)
    qd <= hcnt[number];
else
    qd <= 1'b0;
endmodule