plx_r.v

fpga开发pci的verilog

module plx_r (clk,lrst,ld,ads,lwr,ready,blast,lhold,lholda,la,lwait,ccs,bterm,user_i,user_o,
              fifo_out,rdreq,ReceiveFlag);

input      clk,lrst;
input      ads,lwr,blast,lhold,lwait,user_o;
input [31:0]  fifo_out;
input [13:0]   la;
//input	r_req;

output     ready,lholda,bterm,ccs,user_i;
inout [31:0]  ld;

output rdreq;

output  [7:0] ReceiveFlag;

/****Internal Reg****/
reg   lholda;
reg   rdreq;
reg	  flag,flag1;
reg  [7:0] ReceiveFlag;

wire  ready;

/****Cosntant Output****/
assign   ld  = lwr? 'bz : fifo_out;
assign   ccs = 1'b1;
assign   bterm = 1'b1;
assign   user_i = 1'b1;
/****Generate LholdA****/
always @(posedge clk )
	lholda <= lhold;

/****Generate ready & rdreq****/

always @(posedge clk or negedge lrst)
	begin
		if(!lrst) 
			begin
				flag <= 1'b0;
				rdreq <= 1'b0;
			end
		else if(!ads & !lwr & blast & la[13:10] == 4'b1000)
			begin
				flag <= 1'b1;
				rdreq <= 1'b1;
			end
		else if(ads & !lwr & blast & flag == 1'b1)
			begin
				rdreq <= 1'b1;
			end
		else if(ads & !lwr & !blast & flag == 1'b1)
			begin
				rdreq <= 1'b0;
				flag <= 1'b0;
			end
		else
			begin
				rdreq <= 1'b0;
				flag <= 1'b0;
			end
	end


/****Generate Begin & Stop Signal****/

always @(posedge clk or negedge lrst)
	begin
		if(!lrst) 
			begin
				flag1 <= 1'b0;
				ReceiveFlag <= 8'b0;
			end
		else if(!ads & lwr & blast & la[13:10] == 4'b0001)
			begin
				flag1 <= 1'b1;
			end
		else if(ads & lwr & blast & flag1 == 1'b1 & la[13:10] == 4'b0001)
			begin
				ReceiveFlag[7:0] <= ld[31:24];
			end
		else if(ads & lwr & !blast & flag1 == 1'b1 & la[13:10] == 4'b0001)
			begin
				ReceiveFlag[7:0] <= ld[31:24];
				flag1 <= 1'b0;
			end
		else
			begin
				ReceiveFlag <= ReceiveFlag;
				flag1 <= 1'b0;
			end
	end

//assign ready = !(flag | flag1);

assign ready = 1'b0;	
		

endmodule