with_sdram_daq.tan.summary

fpga开发pci的verilog

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.374 ns
From           : lwr
To             : plx_r:plx9054|ReceiveFlag[4]
From Clock     : 
To Clock       : clkin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.227 ns
From           : fifo1k_32:fifo|dcfifo:dcfifo_component|dcfifo_i9v:auto_generated|dpram_uqm:fiforam|altsyncram_sla1:altsyncram3|ram_block4a3~portb_address_reg9
To             : ld[28]
From Clock     : clkin
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 11.095 ns
From           : lwr
To             : ld[28]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.297 ns
From           : altera_internal_jtag
To             : sld_signaltap:auto_signaltap_0|bypass_reg_out
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clkin'
Slack          : -3.129 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : receiver:receiver0|start_read
To             : datacnt:mydatacnt|STATE[0]
From Clock     : pll0:mypll|altpll:altpll_component|_clk0
To Clock       : clkin
Failed Paths   : 2

Type           : Clock Setup: 'pll0:mypll|altpll:altpll_component|_clk0'
Slack          : 21.695 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : plx_r:plx9054|ReceiveFlag[6]
To             : rec_src:source|vcnt[14]
From Clock     : clkin
To Clock       : pll0:mypll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 93.97 MHz ( period = 10.642 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'clkin'
Slack          : 0.859 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : sdr_sdram:mysdr_sdram|DATAOUT[4]
To             : datacnt:mydatacnt|s_ram_wdb[4]
From Clock     : clkin
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Hold: 'pll0:mypll|altpll:altpll_component|_clk0'
Slack          : 0.971 ns
Required Time  : 20.00 MHz ( period = 50.000 ns )
Actual Time    : N/A
From           : plx_r:plx9054|ReceiveFlag[5]
To             : rec_src:source|vcnt[16]
From Clock     : clkin
To Clock       : pll0:mypll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 2

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