with_sdram_daq.tan.rpt

fpga开发pci的verilog

; Clock Setup: 'altera_internal_jtag~TCKUTAP'             ; N/A       ; None                             ; 93.97 MHz ( period = 10.642 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]                                                                                             ; sld_hub:sld_hub_inst|hub_tdo                  ; altera_internal_jtag~TCKUTAP             ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Hold: 'clkin'                                     ; 0.859 ns  ; 40.00 MHz ( period = 25.000 ns ) ; N/A                              ; sdr_sdram:mysdr_sdram|DATAOUT[4]                                                                                                               ; datacnt:mydatacnt|s_ram_wdb[4]                ; clkin                                    ; clkin                                    ; 0            ;
; Clock Hold: 'pll0:mypll|altpll:altpll_component|_clk0'  ; 0.971 ns  ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; plx_r:plx9054|ReceiveFlag[5]                                                                                                                   ; rec_src:source|vcnt[16]                       ; clkin                                    ; pll0:mypll|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                  ;                                                                                                                                                ;                                               ;                                          ;                                          ; 2            ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                                             ;
+-------------------------------------------------------+--------------------+---------------------------------------+-----------------------------------+-------------+
; Option                                                ; Setting            ; From                                  ; To                                ; Entity Name ;
+-------------------------------------------------------+--------------------+---------------------------------------+-----------------------------------+-------------+
; Device Name                                           ; EP1C6Q240C8        ;                                       ;                                   ;             ;
; Timing Models                                         ; Final              ;                                       ;                                   ;             ;
; Number of source nodes to report per destination node ; 10                 ;                                       ;                                   ;             ;
; Number of destination nodes to report                 ; 10                 ;                                       ;                                   ;             ;
; Number of paths to report                             ; 200                ;                                       ;                                   ;             ;
; Report Minimum Timing Checks                          ; Off                ;                                       ;                                   ;             ;
; Use Fast Timing Models                                ; Off                ;                                       ;                                   ;             ;
; Report IO Paths Separately                            ; Off                ;                                       ;                                   ;             ;
; Default hold multicycle                               ; Same as Multicycle ;                                       ;                                   ;             ;
; Cut paths between unrelated clock domains             ; On                 ;                                       ;                                   ;             ;
; Cut off read during write signal paths                ; On                 ;                                       ;                                   ;             ;
; Cut off feedback from I/O pins                        ; On                 ;                                       ;                                   ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                                       ;                                   ;             ;
; Ignore Clock Settings                                 ; Off                ;                                       ;                                   ;             ;
; Analyze latches as synchronous elements               ; Off                ;                                       ;                                   ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                                       ;                                   ;             ;
; Enable Clock Latency                                  ; Off                ;                                       ;                                   ;             ;
; Cut Timing Path                                       ; On                 ; rdptr_g|power_modified_counter_values ; dffpipe_ws_dgrp|dffpipe10|dffe11a ; dcfifo_i9v  ;
; Cut Timing Path                                       ; On                 ; write_delay_cycle                     ; dffpipe_rs_dgwp|dffpipe6|dffe7a   ; dcfifo_i9v  ;
+-------------------------------------------------------+--------------------+---------------------------------------+-----------------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll0:mypll|altpll:altpll_component|_clk0 ;                    ; PLL output ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clkin    ; 1                     ; 2                   ; -1.885 ns ;              ;
; clkin                                    ;                    ; User Pin   ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP             ;                    ; User Pin   ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll0:mypll|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                            ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+-------------------------+------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                         ; To                      ; From Clock ; To Clock                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+-------------------------+------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 21.695 ns                               ; None                                                ; plx_r:plx9054|ReceiveFlag[6] ; rec_src:source|vcnt[14] ; clkin      ; pll0:mypll|altpll:altpll_component|_clk0 ; 23.115 ns                   ; 26.759 ns                 ; 5.064 ns                ;
; 21.695 ns                               ; None                                                ; plx_r:plx9054|ReceiveFlag[6] ; rec_src:source|vcnt[6]  ; clkin      ; pll0:mypll|altpll:altpll_component|_clk0 ; 23.115 ns                   ; 26.759 ns                 ; 5.064 ns                ;
; 21.695 ns                               ; None                                                ; plx_r:plx9054|ReceiveFlag[6] ; rec_src:source|vcnt[7]  ; clkin      ; pll0:mypll|altpll:altpll_component|_clk0 ; 23.115 ns                   ; 26.759 ns                 ; 5.064 ns                ;
; 21.695 ns                               ; None                                                ; plx_r:plx9054|ReceiveFlag[6] ; rec_src:source|vcnt[8]  ; clkin      ; pll0:mypll|altpll:altpll_component|_clk0 ; 23.115 ns                   ; 26.759 ns                 ; 5.064 ns                ;
; 21.695 ns                               ; None                                                ; plx_r:plx9054|ReceiveFlag[6] ; rec_src:source|vcnt[9]  ; clkin      ; pll0:mypll|altpll:altpll_component|_clk0 ; 23.115 ns                   ; 26.759 ns                 ; 5.064 ns                ;