ram16x8sng.v

FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

//-------------------------------------
//Inferring a 16x8 Single Port Block Ram 
//File name : RAM16x8sng.v
//-------------------------------------
module RAM16x8sng(clk, we, ADDR, Din, Dout);
 parameter DATA_WDTH = 8, ADDR_WDTH = 4;
 
 input        clk; 
 input        we; 
 input  [ADDR_WDTH-1:0] ADDR;     //address for writing data   
 input  [DATA_WDTH-1:0] Din;  
 output [DATA_WDTH-1:0] Dout; 
 
 reg    [DATA_WDTH-1:0] ram [15:0]; 
 reg    [ADDR_WDTH-1:0] read_ADDR; //address for reading data
 
 always @(posedge clk)
  begin 
 	if (we) 
 		ram[ADDR] <= Din; 
 	read_ADDR <= ADDR; 
  end 
 
 assign Dout = ram[read_ADDR]; 
 
endmodule