ram16x8d.v

FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

//-------------------------------------
//Inferring a 16x8 Dual Port Block Ram 
//File name : RAM16x8d.v
//-------------------------------------
module RAM16x8d(clk, we, ADDR, DPR_ADDR, di, SP_OUT, DP_OUT);
 parameter DATA_WDTH = 8, ADDR_WDTH = 4;
 input  clk; 
 input  we; 
 input  [ADDR_WDTH-1:0] ADDR;     //1'st port address  
 input  [ADDR_WDTH-1:0] DPR_ADDR; //2'nd port address
 input  [DATA_WDTH-1:0] di;       //Data input 
 output [DATA_WDTH-1:0] SP_OUT;   //1'st data output 
 output [DATA_WDTH-1:0] DP_OUT;   //2'nd data output 
 
 // 16-byte ram
 reg    [DATA_WDTH-1:0] ram [15:0]; 
 
 always @(posedge clk) begin 
 	if (we) 
 		ram[ADDR] <= di; 
 end 
 
 assign SP_OUT = ram[ADDR]; 
 assign DP_OUT = ram[DPR_ADDR]; 
 
endmodule