ram16x8d_tb.tf

FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg clk;
    reg we;
    reg [3:0] ADDR;
    reg [3:0] DPR_ADDR;
    reg [7:0] di;


// Outputs
    wire [7:0] SP_OUT;
    wire [7:0] DP_OUT;


// Instantiate the UUT
    RAM16x8d uut (
        .clk(clk), 
        .we(we), 
        .ADDR(ADDR), 
        .DPR_ADDR(DPR_ADDR), 
        .di(di), 
        .SP_OUT(SP_OUT), 
        .DP_OUT(DP_OUT)
        );

// Initialize Inputs
initial
 $monitor ($time, "SP_OUT=%h,  DP_OUT=%h, di=%b,  DPR_ADDR=%d, ADDR=%d, we=%b, clk=%b", SP_OUT, DP_OUT, di, DPR_ADDR, ADDR, we, clk);

initial
 begin
   forever #10 clk=~clk;	//Set clock with a period 20 units
 end

initial	//Initialize input signals
 begin
  #0  clk=0; we=0;
  #10 di=8'h11;ADDR=4'h0;we=1; //Write several data into RAM
  #20 we=0;
  #10 di=8'h33;ADDR=4'h1;we=1;
  #20 we=0;
  #10 di=8'h55;ADDR=4'h2;we=1;
  #20 we=0;
  #10 di=8'h77;ADDR=4'h3;we=1;
  #20 we=0;
  #10 di=8'h99;ADDR=4'h4;we=1;
  #20 we=0;
  #10 di=8'hBB;ADDR=4'h5;we=1;
  #20 we=0;
  #10 di=8'hDD;ADDR=4'h6;we=1;
  #20 we=0;
  #10 di=8'hFF;ADDR=4'h7;we=1;
  #20 we=0;
  #20 DPR_ADDR=4'h0;	      //Read data from RAM to the 2'nd port
  #20 DPR_ADDR=4'h1;
  #20 DPR_ADDR=4'h2;
  #20 DPR_ADDR=4'h3;
  #20 DPR_ADDR=4'h4;
  #20 DPR_ADDR=4'h5;
  #20 DPR_ADDR=4'h6;
  #20 DPR_ADDR=4'h7;
 end

initial #500 $finish;        //Complete simulation after 500 units

endmodule