display.vhd

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity display is
	port(
		clk:in std_logic;
		data:std_logic_vector(3 downto 0);
		q:out std_logic_vector(6 downto 0)
		);
end entity;
architecture display_xht of display is
begin
	process(clk,data)
	begin
		if rising_edge(clk) then
			case data is
				when "0000"=>q<="0111111";
				when "0001"=>q<="0110000";
				when "0010"=>q<="1101101";
				when "0011"=>q<="1111001";
				when "0100"=>q<="0110011";
				when "0101"=>q<="1011011";
				when "0110"=>q<="0011111";
				when "0111"=>q<="1110000";
				when "1000"=>q<="1111111";
				when "1001"=>q<="1110011";  --9
				when "1010"=>q<="1110111";
				when "1011"=>q<="1111111";
				when "1100"=>q<="1001110"; --c
				when "1101"=>q<="0000000";--d
				when "1110"=>q<="1001111";--
				when "1111"=>q<="1000111";
				when others=>q<="0000000";
			end case;
		end if;
	end process;
end display_xht;