key_prog.tan.rpt

简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.

; Clock Setup: 'clk'                                                                                                                                                                                                   ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                   ; To                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[2] ; key_scan:inst2|temp[1] ; clk        ; clk      ; None                        ; None                      ; 1.302 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[2] ; key_scan:inst2|temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.302 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[2] ; key_scan:inst2|temp[2] ; clk        ; clk      ; None                        ; None                      ; 1.297 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[2] ; key_scan:inst2|temp[0] ; clk        ; clk      ; None                        ; None                      ; 1.297 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[0] ; key_scan:inst2|temp[1] ; clk        ; clk      ; None                        ; None                      ; 1.173 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[0] ; key_scan:inst2|temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.172 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[0] ; key_scan:inst2|temp[2] ; clk        ; clk      ; None                        ; None                      ; 1.165 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[0] ; key_scan:inst2|temp[0] ; clk        ; clk      ; None                        ; None                      ; 1.163 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[1] ; key_scan:inst2|temp[0] ; clk        ; clk      ; None                        ; None                      ; 1.056 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[1] ; key_scan:inst2|temp[2] ; clk        ; clk      ; None                        ; None                      ; 1.055 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[1] ; key_scan:inst2|temp[3] ; clk        ; clk      ; None                        ; None                      ; 1.052 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[1] ; key_scan:inst2|temp[1] ; clk        ; clk      ; None                        ; None                      ; 1.050 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[3] ; key_scan:inst2|temp[2] ; clk        ; clk      ; None                        ; None                      ; 0.910 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[3] ; key_scan:inst2|temp[0] ; clk        ; clk      ; None                        ; None                      ; 0.910 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[3] ; key_scan:inst2|temp[1] ; clk        ; clk      ; None                        ; None                      ; 0.902 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; key_scan:inst2|temp[3] ; key_scan:inst2|temp[3] ; clk        ; clk      ; None                        ; None                      ; 0.902 ns                ;
+-------+------------------------------------------------+------------------------+------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------+
; tco                                                                                 ;
+-------+--------------+------------+------------------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From                   ; To        ; From Clock ;
+-------+--------------+------------+------------------------+-----------+------------+
; N/A   ; None         ; 7.106 ns   ; key_scan:inst2|temp[2] ; key_in[2] ; clk        ;
; N/A   ; None         ; 6.663 ns   ; key_scan:inst2|temp[0] ; key_in[0] ; clk        ;
; N/A   ; None         ; 6.662 ns   ; key_scan:inst2|temp[1] ; key_in[1] ; clk        ;
; N/A   ; None         ; 6.662 ns   ; key_scan:inst2|temp[3] ; key_in[3] ; clk        ;
+-------+--------------+------------+------------------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Oct 23 09:48:24 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off key_prog -c key_prog --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "key_scan:inst2|temp[2]" and destination register "key_scan:inst2|temp[1]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.302 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2|temp[2]'
            Info: 2: + IC(0.564 ns) + CELL(0.738 ns) = 1.302 ns; Loc. = LC_X1_Y5_N2; Fanout = 5; REG Node = 'key_scan:inst2|temp[1]'
            Info: Total cell delay = 0.738 ns ( 56.68 % )
            Info: Total interconnect delay = 0.564 ns ( 43.32 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.170 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y5_N2; Fanout = 5; REG Node = 'key_scan:inst2|temp[1]'
                Info: Total cell delay = 2.180 ns ( 68.77 % )
                Info: Total interconnect delay = 0.990 ns ( 31.23 % )
            Info: - Longest clock path from clock "clk" to source register is 3.170 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2|temp[2]'
                Info: Total cell delay = 2.180 ns ( 68.77 % )
                Info: Total interconnect delay = 0.990 ns ( 31.23 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "key_in[2]" through register "key_scan:inst2|temp[2]" is 7.106 ns
    Info: + Longest clock path from clock "clk" to source register is 3.170 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2|temp[2]'
        Info: Total cell delay = 2.180 ns ( 68.77 % )
        Info: Total interconnect delay = 0.990 ns ( 31.23 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.712 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2|temp[2]'
        Info: 2: + IC(1.588 ns) + CELL(2.124 ns) = 3.712 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'key_in[2]'
        Info: Total cell delay = 2.124 ns ( 57.22 % )
        Info: Total interconnect delay = 1.588 ns ( 42.78 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Oct 23 09:48:25 2006
    Info: Elapsed time: 00:00:01