key_prog.tan.qmsg

简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register key_scan:inst2\|temp\[2\] key_scan:inst2\|temp\[1\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"key_scan:inst2\|temp\[2\]\" and destination register \"key_scan:inst2\|temp\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.302 ns + Longest register register " "Info: + Longest register to register delay is 1.302 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_scan:inst2\|temp\[2\] 1 REG LC_X1_Y5_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2\|temp\[2\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "" { key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.738 ns) 1.302 ns key_scan:inst2\|temp\[1\] 2 REG LC_X1_Y5_N2 5 " "Info: 2: + IC(0.564 ns) + CELL(0.738 ns) = 1.302 ns; Loc. = LC_X1_Y5_N2; Fanout = 5; REG Node = 'key_scan:inst2\|temp\[1\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "1.302 ns" { key_scan:inst2|temp[2] key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 56.68 % " "Info: Total cell delay = 0.738 ns ( 56.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.564 ns 43.32 % " "Info: Total interconnect delay = 0.564 ns ( 43.32 % )" {  } {  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "1.302 ns" { key_scan:inst2|temp[2] key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.302 ns" { key_scan:inst2|temp[2] key_scan:inst2|temp[1] } { 0.000ns 0.564ns } { 0.000ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "" { clk } "NODE_NAME" } "" } } { "key_prog.bdf" "" { Schematic "D:/key_prog/key_prog.bdf" { { 192 -136 32 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns key_scan:inst2\|temp\[1\] 2 REG LC_X1_Y5_N2 5 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y5_N2; Fanout = 5; REG Node = 'key_scan:inst2\|temp\[1\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "1.701 ns" { clk key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.77 % " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns 31.23 % " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "" { clk } "NODE_NAME" } "" } } { "key_prog.bdf" "" { Schematic "D:/key_prog/key_prog.bdf" { { 192 -136 32 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns key_scan:inst2\|temp\[2\] 2 REG LC_X1_Y5_N6 5 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2\|temp\[2\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "1.701 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.77 % " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns 31.23 % " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[2] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[2] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "1.302 ns" { key_scan:inst2|temp[2] key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.302 ns" { key_scan:inst2|temp[2] key_scan:inst2|temp[1] } { 0.000ns 0.564ns } { 0.000ns 0.738ns } } } { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[2] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "" { key_scan:inst2|temp[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { key_scan:inst2|temp[1] } {  } {  } } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk key_in\[2\] key_scan:inst2\|temp\[2\] 7.106 ns register " "Info: tco from clock \"clk\" to destination pin \"key_in\[2\]\" through register \"key_scan:inst2\|temp\[2\]\" is 7.106 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "" { clk } "NODE_NAME" } "" } } { "key_prog.bdf" "" { Schematic "D:/key_prog/key_prog.bdf" { { 192 -136 32 208 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns key_scan:inst2\|temp\[2\] 2 REG LC_X1_Y5_N6 5 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2\|temp\[2\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "1.701 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.77 % " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns 31.23 % " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[2] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.712 ns + Longest register pin " "Info: + Longest register to pin delay is 3.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_scan:inst2\|temp\[2\] 1 REG LC_X1_Y5_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N6; Fanout = 5; REG Node = 'key_scan:inst2\|temp\[2\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "" { key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "key_scan.vhd" "" { Text "D:/key_prog/key_scan.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(2.124 ns) 3.712 ns key_in\[2\] 2 PIN PIN_50 0 " "Info: 2: + IC(1.588 ns) + CELL(2.124 ns) = 3.712 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'key_in\[2\]'" {  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.712 ns" { key_scan:inst2|temp[2] key_in[2] } "NODE_NAME" } "" } } { "key_prog.bdf" "" { Schematic "D:/key_prog/key_prog.bdf" { { 80 232 408 96 "key_in\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 57.22 % " "Info: Total cell delay = 2.124 ns ( 57.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns 42.78 % " "Info: Total interconnect delay = 1.588 ns ( 42.78 % )" {  } {  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.712 ns" { key_scan:inst2|temp[2] key_in[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.712 ns" { key_scan:inst2|temp[2] key_in[2] } { 0.000ns 1.588ns } { 0.000ns 2.124ns } } }  } 0}  } { { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.170 ns" { clk key_scan:inst2|temp[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 key_scan:inst2|temp[2] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/key_prog/db/key_prog_cmp.qrpt" "" { Report "D:/key_prog/db/key_prog_cmp.qrpt" Compiler "key_prog" "UNKNOWN" "V1" "D:/key_prog/db/key_prog.quartus_db" { Floorplan "D:/key_prog/" "" "3.712 ns" { key_scan:inst2|temp[2] key_in[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.712 ns" { key_scan:inst2|temp[2] key_in[2] } { 0.000ns 1.588ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 23 09:48:25 2006 " "Info: Processing ended: Mon Oct 23 09:48:25 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}