📄 key_out.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity key_out is
port(
clk:in std_logic;
-- scan_in:in std_logic_vector(3 downto 0);
scan_out:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0)
);
end entity;
architecture rt1 of key_out is
signal temp:std_logic_vector(3 downto 0);
signal scan_in: std_logic_vector(3 downto 0);
begin
process (clk,scan_in)
begin
if rising_edge(clk) then
if (scan_in<="0001") then
if(scan_out<="0001") then
temp<="0000";
elsif (scan_out<="0010")then
temp<="0100";
elsif (scan_out<="0100")then
temp<="1000";
elsif (scan_out<="1000")then
temp<="1100";
-- else temp<="zzzz";
end if;
elsif (scan_in<="0010") then
if(scan_out<="0001") then
temp<="0001";
elsif (scan_out<="0010")then
temp<="0101";
elsif (scan_out<="0100")then
temp<="1001";
elsif (scan_out<="1000")then
temp<="1101";
-- else temp<="zzzz";
end if;
elsif (scan_in<="0100") then
if(scan_out<="0001") then
temp<="0010";
elsif (scan_out<="0010")then
temp<="0110";
elsif (scan_out<="0100")then
temp<="1010";
elsif (scan_out<="1000")then
temp<="1110";
-- else temp<="zzzz";
end if;
elsif (scan_in<="1000") then
if(scan_out<="0001") then
temp<="0011";
elsif (scan_out<="0010")then
temp<="0111";
elsif (scan_out<="0100")then
temp<="1011";
elsif (scan_out<="1000")then
temp<="1111";
-- else temp<="zzzz";
end if;
end if;
end if;
end process;
q<=temp;
end rt1;
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