📄 key_scan.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.STD_LOGIC_ARITH.ALL;
entity key_scan is
port(
clk:in std_logic;
pin:out std_logic_vector(3 downto 0)
);
end entity;
architecture scan of key_scan is
signal temp:std_logic_vector(3 downto 0);
begin
-- temp<="0000";
process(clk)
begin
if rising_edge(clk) then
case temp is
when "0001"=>temp<="0010";
when "0010"=>temp<="0100";
when "0100"=>temp<="1000";
when "1000"=>temp<="0001";
when others=>temp<="0001";
end case;
-- if temp<="0000" then
-- temp<="0010";
-- elsif temp<="0010" then
-- temp<="0100";
-- elsif temp<="0010" then
-- temp<="0100";
--- elsif temp<="0100" then
-- temp<="1000";
-- elsif temp<="1000" then
-- temp<="0001";
-- end if;
-- temp<=rol temp 1;
end if;
end process;
pin<=temp;
end scan;
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