key_prog.fit.rpt

简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.

+----------------------------------+
; Non-Global High Fan-Out Signals  ;
+------------------------+---------+
; Name                   ; Fan-Out ;
+------------------------+---------+
; key_scan:inst2|temp[0] ; 5       ;
; key_scan:inst2|temp[1] ; 5       ;
; key_scan:inst2|temp[2] ; 5       ;
; key_scan:inst2|temp[3] ; 5       ;
+------------------------+---------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; C4s                        ; 1 / 30,600 ( < 1 % ) ;
; Direct links               ; 3 / 43,552 ( < 1 % ) ;
; Global clocks              ; 1 / 8 ( 12 % )       ;
; LAB clocks                 ; 1 / 312 ( < 1 % )    ;
; LUT chains                 ; 0 / 10,854 ( 0 % )   ;
; Local interconnects        ; 4 / 43,552 ( < 1 % ) ;
; M4K buffers                ; 0 / 1,872 ( 0 % )    ;
; R4s                        ; 0 / 28,560 ( 0 % )   ;
+----------------------------+----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 4.00) ; Number of LABs  (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 1                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+------------------------------------+-----------------------------+
; 1 Clock                            ; 1                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 4.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 4.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 0                           ;
; 2                                               ; 0                           ;
; 3                                               ; 0                           ;
; 4                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 1.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Oct 23 09:47:54 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off key_prog -c key_prog
Info: Selected device EP1C12Q240C8 for design "key_prog"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C6Q240C8 is compatible
Info: No exact pin location assignment(s) for 16 pins of 16 total pins
    Info: Pin key_in[3] not assigned to an exact location on the device
    Info: Pin key_in[2] not assigned to an exact location on the device
    Info: Pin key_in[1] not assigned to an exact location on the device
    Info: Pin key_in[0] not assigned to an exact location on the device
    Info: Pin soeplay[6] not assigned to an exact location on the device
    Info: Pin soeplay[5] not assigned to an exact location on the device
    Info: Pin soeplay[4] not assigned to an exact location on the device
    Info: Pin soeplay[3] not assigned to an exact location on the device
    Info: Pin soeplay[2] not assigned to an exact location on the device
    Info: Pin soeplay[1] not assigned to an exact location on the device
    Info: Pin soeplay[0] not assigned to an exact location on the device
    Info: Pin key_out[3] not assigned to an exact location on the device
    Info: Pin key_out[2] not assigned to an exact location on the device
    Info: Pin key_out[1] not assigned to an exact location on the device
    Info: Pin key_out[0] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "clk" to use Global clock in PIN 29
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 15 (unused