key_prog.map.rpt

简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.

+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary              ;
+---------------------------------+------------------------+
; Resource                        ; Usage                  ;
+---------------------------------+------------------------+
; Total logic elements            ; 4                      ;
; Total combinational functions   ; 4                      ;
;     -- Total 4-input functions  ; 4                      ;
;     -- Total 3-input functions  ; 0                      ;
;     -- Total 2-input functions  ; 0                      ;
;     -- Total 1-input functions  ; 0                      ;
;     -- Total 0-input functions  ; 0                      ;
; Combinational cells for routing ; 0                      ;
; Total registers                 ; 4                      ;
; I/O pins                        ; 16                     ;
; Maximum fan-out node            ; key_scan:inst2|temp[3] ;
; Maximum fan-out                 ; 5                      ;
; Total fan-out                   ; 24                     ;
; Average fan-out                 ; 1.20                   ;
+---------------------------------+------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
; |key_prog                  ; 4 (0)       ; 4            ; 0           ; 16   ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 0 (0)           ; |key_prog                ;
;    |key_scan:inst2|        ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |key_prog|key_scan:inst2 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/key_prog/key_prog.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Oct 23 09:47:46 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key_prog -c key_prog
Info: Found 2 design units, including 1 entities, in source file key_scan.vhd
    Info: Found design unit 1: key_scan-scan
    Info: Found entity 1: key_scan
Info: Found 2 design units, including 1 entities, in source file key_out.vhd
    Info: Found design unit 1: key_out-rt1
    Info: Found entity 1: key_out
Info: Found 1 design units, including 1 entities, in source file key_prog.bdf
    Info: Found entity 1: key_prog
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-display_xht
    Info: Found entity 1: display
Info: Elaborating entity "key_prog" for the top level hierarchy
Info: Elaborating entity "key_scan" for hierarchy "key_scan:inst2"
Info: Elaborating entity "display" for hierarchy "display:inst"
Info: VHDL Case Statement information at display.vhd(32): OTHERS choice is never selected
Info: Elaborating entity "key_out" for hierarchy "key_out:inst4"
Warning: VHDL Signal Declaration warning at key_out.vhd(15): used implicit default value for signal "scan_in" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning: Tied undriven net "temp[3]" at key_out.vhd(14) to X
Warning: Tied undriven net "temp[2]" at key_out.vhd(14) to X
Warning: Tied undriven net "temp[1]" at key_out.vhd(14) to X
Warning: Tied undriven net "temp[0]" at key_out.vhd(14) to X
Info: Power-up level of register "display:inst|q[5]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "display:inst|q[5]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "display:inst|q[4]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "display:inst|q[4]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "display:inst|q[3]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "display:inst|q[3]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "display:inst|q[2]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "display:inst|q[2]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "display:inst|q[1]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "display:inst|q[1]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "display:inst|q[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "display:inst|q[0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "display:inst|q[6]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "soeplay[6]" stuck at GND
    Warning: Pin "soeplay[5]" stuck at VCC
    Warning: Pin "soeplay[4]" stuck at VCC
    Warning: Pin "soeplay[3]" stuck at VCC
    Warning: Pin "soeplay[2]" stuck at VCC
    Warning: Pin "soeplay[1]" stuck at VCC
    Warning: Pin "soeplay[0]" stuck at VCC
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "key_out[3]"
    Warning: No output dependent on input pin "key_out[2]"
    Warning: No output dependent on input pin "key_out[1]"
    Warning: No output dependent on input pin "key_out[0]"
Info: Implemented 20 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 11 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Processing ended: Mon Oct 23 09:47:51 2006
    Info: Elapsed time: 00:00:06