a.ptf

简单易懂的4*4键盘扫描及显示程序。对编写其他形式的键盘扫描程序有一定的指导意义.

               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
            # next brace matches DISPLAY
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            # file descriptors are really just suffixes for perl
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
         # next brace matches SIMULATION
      }
      # next brace matches MODULE_DEFAULTS
   }
   MODULE tri_state_bridge_0
   {
      class = "altera_avalon_tri_state_bridge";
      class_version = "2.0";
      SLAVE avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Register_Outgoing_Signals = "1";
            Register_Incoming_Signals = "1";
            MASTERED_BY cpu_0/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Bridges_To = "avalon_slave";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "0";
         }
      }
   }
   MODULE dma_0
   {
      class = "altera_avalon_dma";
      class_version = "5.0";
      MASTER read_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Max_Address_Width = "32";
            Data_Width = "-1";
            Do_Stream_Reads = "1";
            Is_Readable = "1";
            Is_Writable = "0";
            Maximum_Burst_Size = "1";
         }
      }
      MASTER write_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Max_Address_Width = "32";
            Data_Width = "-1";
            Do_Stream_Writes = "1";
            Is_Readable = "0";
            Is_Writable = "1";
            Maximum_Burst_Size = "1";
         }
      }
      SLAVE control_port_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "0";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         readaddress_reset_value = "0x0";
         writeaddress_reset_value = "0x0";
         length_reset_value = "0x0";
         # Note: control register reset values are specified
         # on a per-bit basis.
         # Individual specifications for control register bits:
         control_byte_reset_value = "0";
         control_hw_reset_value = "0";
         control_word_reset_value = "1";
         control_go_reset_value = "0";
         control_i_en_reset_value = "0";
         control_reen_reset_value = "0";
         control_ween_reset_value = "0";
         control_leen_reset_value = "1";
         control_rcon_reset_value = "0";
         control_wcon_reset_value = "0";
         control_doubleword_reset_value = "0";
         control_quadword_reset_value = "0";
         # A minimum for the width of the length register can be specified:
         lengthwidth = "13";
         burst_enable = "0";
         # A minimum size for the fifo depth can be specified:
         fifo_in_logic_elements = "1";
         allow_byte_transactions = "1";
         allow_hw_transactions = "1";
         allow_word_transactions = "1";
         allow_doubleword_transactions = "1";
         allow_quadword_transactions = "1";
         max_burst_size = "";
      }
   }
   MODULE cfi_flash_1
   {
      class = "altera_avalon_cfi_flash";
      class_version = "1.1";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "8";
               is_shared = "1";
               direction = "inout";
               type = "data";
            }
            PORT address
            {
               width = "23";
               is_shared = "1";
               direction = "input";
               type = "address";
            }
            PORT read_n
            {
               width = "1";
               is_shared = "1";
               direction = "input";
               type = "read_n";
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "U6";
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Nonvolatile_Storage = "1";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Base_Address = "0x80000000";
            Data_Width = "8";
            Address_Width = "23";
            Simulation_Num_Lanes = "1";
            Convert_Xs_To_0 = "1";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Setup_Time = "40ns";
            Hold_Time = "40ns";
            Address_Span = "8388608";
            MASTERED_BY tri_state_bridge_0/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Make_Memory_Model = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "40";
         Wait_Value = "160";
         Hold_Value = "40";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "8388608";
      }
   }
   MODULE generic_avalon_sram_0
   {
      class = "generic_avalon_sram";
      class_version = "2.0";
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "8";
               is_shared = "1";
               direction = "inout";
               type = "data";
            }
            PORT address
            {
               width = "15";
               is_shared = "1";
               direction = "input";
               type = "address";
            }
            PORT oe_n
            {
               width = "1";
               is_shared = "1";
               direction = "input";
               type = "read_n";
            }
            PORT we_n
            {
               width = "1";
               is_shared = "1";
               direction = "input";
               type = "write_n";
            }
            PORT ce_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
            }
            PORT bc_n
            {
               width = "2";
               is_shared = "1";
               direction = "input";
               #type = "byteenable_n";
               type = "";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Data_Width = "8";
            Address_Width = "15";
            Has_IRQ = "0";
            #Read_Wait_States = "5";
            #Write_Wait_States = "4";
            Base_Address = "--unknown--";
            Read_Wait_States = "0";
            Write_Wait_States = "0";
            MASTERED_BY tri_state_bridge_0/tristate_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "NC";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Make_Memory_Model = "0";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Clock_Source = "clk";
      }
   }
}