📄 a.ptf
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{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
}
MODULE cfi_flash_0
{
class = "altera_avalon_cfi_flash";
class_version = "1.1";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "8";
is_shared = "1";
direction = "inout";
type = "data";
}
PORT address
{
width = "31";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Nonvolatile_Storage = "1";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "31";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "40ns";
Hold_Time = "40ns";
Address_Span = "2147483648";
MASTERED_BY tri_state_bridge_0/tristate_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Make_Memory_Model = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "2147483648";
}
}
MODULE pio_0
{
class = "altera_avalon_pio";
class_version = "2.2";
HDL_INFO
{
# The list of files associated with this module (for synthesis
# and other purposes) depends on the users' wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the
# various filenames are known.
}
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the ports are known.
#
# The top-level ports must be listed here so that
# the SOPC Builder pin assigner knows about them.
# The UI may enable some combination of these ports, which
# allows pin assignments to be made for the enabled ones.
PORT in_port
{
direction = "input";
Is_Enabled = "1";
width = "8";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "8";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "8";
}
}
SLAVE s1
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the ports are known.
#
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "1";
Address_Width = "2";
Data_Width = "8";
Base_Address = "";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "0";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 8-bit PIO using <br>
input pins with edge type RISING and interrupt source LEVEL
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "1";
edge_type = "RISING";
irq_type = "LEVEL";
}
}
MODULE jtag_uart_0
{
class = "altera_avalon_jtag_uart";
class_version = "1.0";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
# sld_node_ver = "1"; # SLD Node Version
# sld_node_id = "128";# SLD Node Identifier 0x80
# sld_mfg_id = "110";# SLD MFG Identifier 0x6e for Altera
# instance_id = "0"; # SLD Hub Instance ID for jtag_uart
# The sld_node_ver is NOT included in the _Base_Id to spare confusion in sw.
# Otherwise, the _Base_Id would be "0x0C006E"
JTAG_Hub_Base_Id = "0x04006E";
# sld_* composited as 24 bit hex
JTAG_Hub_Instance_Id = "0";
# set via function during generate
Connection_Limit = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Base_Address = "";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
# Date_Modified = "--unknown--";
Clock_Source = "clk";
View
{
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
<br>Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
# max entries in write fifo
read_depth = "64";
# max entries in read fifo
write_threshold = "8";
# Chars remaining in write fifo to trigger irq
read_threshold = "8";
# Spaces in read fifo to trigger irq
read_char_stream = "";
# simulated character input stream.
showascii = "1";
# (re)set by $INO/enable during finish
read_le = "0";
# 1=>use_eab=off; 0=>use_eab=on
write_le = "0";
# 1=>use_eab=off; 0=>use_eab=on
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
# These signals are "of interest" and are added to the waveform window, etc.
# The name of the section (e.g. "a2" or "f") doesn't "mean" anything, except
# that the signals will be displayed in the waveform window in-order, as
# sorted by these otherwise-meaningless names.
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
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