📄 a.ptf
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Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
# only self-component-mastered
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "";
Is_Memory_Device = "1";
# FIXME. Needed for now.
Is_Readable = "1";
Is_Writeable = "1";
Is_Printable_Device = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
# JTAG_Hub_Base_ID is :
# (Node_Ver << 19) +
# (0x22 << 11) + # Node ID
# (0x46 << 0 ) # Mfg_ID
#
# For Nios II 1.0:
# Node_Ver = 0, JTAG_Hub_Base_ID = 0x011046 = 69702
# For Nios II 1.01 and 1.1:
# Node_Ver = 1, JTAG_Hub_Base_ID = 0x091046 = 593990
# For Nios II 5.0:
# Node_Ver = 2, JTAG_Hub_Base_ID = 0x111046 = 1118278
#
# If you update this value, you must also change the value
# assigned in enforce_jtag_base_id_replacement later in this
# PTF file.
JTAG_Hub_Base_Id = "1118278";
JTAG_Hub_Instance_Id = "0";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
PORT_WIRING
{
PORT jtag_debug_trigout
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "0";
}
PORT clkx2
{
width = "1";
direction = "input";
Is_Enabled = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
# Invokes Visual Stdio Perl debugger for cpu_core_select.pl
asp_debug = "0";
# Invokes Visual Stdio Perl debugger for cpu_core.pl
# This is normally what you want.
asp_core_debug = "0";
CPU_Architecture = "nios2";
# CONSTANT CONSTANT
# User Settings
do_generate = "1";
# ALWAYS GENERATE WHEN ASKED
cpu_selection = "e";
# {e, s, f, x4} (used by GUI)
CPU_Implementation = "tiny";
# {tiny, small, fast, x4}
# Caches / Tightly Coupled Memories page
gui_include_tightly_coupled_instruction_masters = "0";
# {0, 1}
gui_num_tightly_coupled_instruction_masters = "1";
# {1,2,3,4}
gui_omit_avalon_data_master = "0";
# {0, 1}
gui_include_tightly_coupled_data_masters = "0";
# {0, 1}
gui_num_tightly_coupled_data_masters = "1";
# {1,2,3,4}
num_tightly_coupled_instruction_masters = "0";
# {0, 1, 2, 3, 4}
num_tightly_coupled_data_masters = "0";
# {0, 1, 2, 3, 4}
cache_has_dcache = "0";
# {0, 1}
cache_has_icache = "0";
# {0, 1}
cache_dcache_size = "2048";
# {0, 512, 1024, ... 65536}
cache_icache_size = "4096";
# {0, 512, 1024, ... 65536}
cache_dcache_line_size = "4";
# {4, 16, 32}
cache_icache_line_size = "32";
# {32}
cache_dcache_bursts = "0";
# {0, 1}
cache_icache_burst_type = "none";
# {none, sequential, interleaved}
cache_dcache_ram_block_type = "AUTO";
# {AUTO, M4K, M-RAM}
cache_icache_ram_block_type = "AUTO";
# {AUTO, M4K, M-RAM}
include_debug = "0";
# LEAVE AS 0 (pre-OCI debug solution)
include_trace = "0";
# ALWAYS SET TO 0 (pre-OCI trace solution)
include_oci = "1";
# {0, 1}. must be 0 if "include_third_party_debug_port" is 1.
include_third_party_debug_port = "0";
# {0, 1}. must be 0 if "include_oci" is 1.
debug_level = "2";
# {1, 2, 3, 4, 5} (used by GUI)
oci_offchip_trace = "0";
# {0, 1} Support off-chip trace signals (FS2 box required)
oci_onchip_trace = "0";
# {0, 1} Support On-chip trace memory
oci_data_trace = "0";
# {0, 1} Support data trace
oci_trace_addr_width = "7";
# {7 ... 16}
oci_num_xbrk = "0";
# {0, 1, 4} Number of instruction hw breakpoints
oci_num_dbrk = "0";
# {0, 2, 4} Number of data hw watchpoints
oci_dbrk_trace = "0";
# {0, 1} Enable watchpoints to trigger trace
oci_dbrk_pairs = "0";
# {0, 1} Enable watchpoints to work in pairs
oci_num_pm = "0";
# {0, 1, 2} Number of performance monitors
oci_pm_width = "40";
# {32..65} Number of bits in performance monitor counter
oci_debugreq_signals = "0";
# (Leave as 0 because no one seems to use it.)
oci_trigger_arming = "1";
# {0, 1} Enable trigger states for trigger arming
oci_embedded_pll = "1";
# {0, 1} For Cyclone example design.
hardware_multiply_present = "0";
# {0, 1}
hardware_divide_present = "0";
# {0, 1}
# If hardware_multiply_present, then these are interesting.
gui_hardware_multiply_setting = "no_mul_small_le_shift";
hardware_multiply_uses_les = "0";
# {0, 1} GUI combo setting
hardware_multiply_omits_msw = "1";
# {0, 1}
# Enumerated type is defined with the definitions below.
hardware_multiply_impl = "no_mul";
gui_hardware_divide_setting = "0";
# {0, 1} (or "" to force
# initialization)
# $OCI_SBI/Is_Enabled = {0, 1}
# Binding Page
reset_slave = "generic_avalon_sram_0/s1";
# Binding
reset_offset = "0x00000000";
# Binding
exc_slave = "generic_avalon_sram_0/s1";
# Binding
exc_offset = "0x00000020";
# Binding
break_slave = "cpu_0/jtag_debug_module";
# Binding
break_offset = "0x00000020";
# Binding # FIXME make 0x20
break_slave_override = "";
# Binding
break_offset_override = "0x20";
# Binding
legacy_sdk_support = "0";
# Binding
# This flag is set manually in the system PTF file
# to show a page of settings for unreleased features.
altera_show_unreleased_features = "0";
# {0, 1}
# Altera Unreleased Features Settings
full_waveform_signals = "0";
# {0, 1}
illegal_instructions_trap = "0";
# {0, 1}
gui_branch_prediction_type = "Automatic";
branch_prediction_type = "Dynamic";
bht_ptr_sz = "8";
# {8, 9, 10, 11}
bht_index_pc_only = "0";
# {0, 1}
shift_rot_impl = "small_le_shift";
mmu_present = "0";
# {0, 1}
process_id_num_bits = "10";
# {8 to 14}
dtlb_ptr_sz = "7";
# {7, 8, 9, 10}
dtlb_num_ways = "4";
# {2,4,8}
udtlb_num_entries = "6";
# {2,4,6,8}
itlb_ptr_sz = "7";
# {7, 8, 9, 10}
itlb_num_ways = "4";
# {2,4,8}
uitlb_num_entries = "4";
# {2,4,6,8}
fast_tlb_miss_exc_slave = "";
# Binding
fast_tlb_miss_exc_offset = "0x0";
# Binding
# Features that are supported now, but related unreleased-features
# settings are ignored and generate warnings in this release.
# When we omit the warnings, we can delete these settings.
cache_omit_dcache = "0";
# {0, 1}
cache_omit_icache = "0";
# {0, 1}
omit_instruction_master = "0";
# {0, 1}
omit_data_master = "0";
# {0, 1}
# This flag is set manually in the system PTF file
# to enable features related to Altera internal testing.
altera_internal_test = "0";
# {0, 1}
# Altera Internal Test Settings
performance_counters_present = "0";
# {0, 1}
performance_counters_width = "32";
# {16, 24, 32}
ras_ptr_sz = "4";
# {3, 4, 5}
jtb_ptr_sz = "5";
# {5, 6, 7, 8}
ibuf_ptr_sz = "4";
# {2, 3, 4, 5}
always_encrypt = "1";
# {0, 1}
activate_model_checker = "0";
# {0, 1}
activate_monitors = "1";
# {0, 1}
activate_test_end_checker = "0";
# {0, 1}
activate_trace = "1";
# {0, 1}
clear_x_bits_ld_non_bypass = "1";
# {0, 1}
bit_31_bypass_dcache = "1";
# {0, 1}
always_bypass_dcache = "0";
# {0, 1}
hdl_sim_caches_cleared = "1";
# {0, 1}
consistent_synthesis = "0";
# {0, 1}
hbreak_test = "0";
# {0, 1}
allow_full_address_range = "0";
# {0, 1}
# ISS options
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
# Assignments associated with the flash and EPCS boot copiers.
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "0";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "0";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "4";
comment = "Size in bytes of each dcache line";
}
CONSTANT nasys_dcache_line_size_log2
{
value = "2";
comment = "Log2 size in bytes of each dcache line";
}
}
license_status = "";
germs_monitor_id = "";
}
SYSTEM_BUILDER_INFO
{
Parameters_Signature = "";
Is_CPU = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "STRATIX,STRATIXII,CYCLONE,CYCLONEII";
# Controls the prefix of the default instance name chosen
# by SOPC builder (it adds a unique numeric suffix).
Default_Module_Name = "cpu";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
Settings_Summary = "Nios II/e
<br> JTAG Debug Module
";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "2.1";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
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