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SYSTEM a
{
System_Wizard_Version = "5.00";
System_Wizard_Build = "148";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "1";
hardcopy_compatible = "0";
board_class = "altera_nios_eval_board_cyclone_1c12";
CLOCKS
{
clk = "50000000";
}
hdl_language = "vhdl";
device_family_id = "CYCLONE";
view_master_columns = "1";
view_master_priorities = "0";
name_column_width = "195";
desc_column_width = "196";
bustype_column_width = "0";
base_column_width = "75";
clock_column_width = "80";
end_column_width = "75";
view_frame_window = "maximized";
BOARD_INFO
{
CONFIGURATION epcs
{
length = "";
menu_position = "1";
offset = "0x0";
reference_designator = "U2";
}
JTAG_device_index = "1";
REFDES U2
{
base = "0x00060000";
}
REFDES U6
{
base = "0x00800000";
}
altera_avalon_cfi_flash
{
reference_designators = "U6";
}
altera_avalon_epcs_flash_controller
{
reference_designators = "U2";
}
class = "altera_nios_eval_board_cyclone_1c12";
class_version = "5.0";
device_family = "CYCLONE";
quartus_pgm_file = "system/altera_nios_eval_board_cyclone_1c12.sof";
quartus_project_file = "system/altera_nios_eval_board_cyclone_1c12.qpf";
reference_designators = "U2,U6";
sopc_system_file = "system/altera_nios_eval_board_cyclone_1c12.ptf";
}
}
MODULE cpu_0
{
class = "altera_nios2";
class_version = "5.0";
iss_model_name = "altera_nios2";
HDL_INFO
{
# The list of files associated with this module (for synthesis
# and other purposes) depends on the users' wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the
# various filenames are known.
}
MASTER instruction_master
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
# This is only for hbreak test bench, not for human consumption
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
# Burst parameters. Only used if I-cache present.
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Linewrap_Bursts = "";
Interleave_Bursts = "";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_master
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
# Burst parameters. Only used if D-cache present.
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
}
}
MASTER data_master2
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
}
}
MASTER tightly_coupled_data_master_0
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
# The number and kind of ports that appear on this module
# depends on the user's wizard-choices.
# This section will be filled-in by the Generator_Program after
# the module logic has been created and the ports are known.
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
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