control.rpt

这是一个DDS程序,用VHDL编写,实现的是一个频率可调的方波

  _EQ010 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17 & !count18 & !count19 & !count116
         # !count18 & !count19 &  count116 & !_LC014;

-- Node name is ':28' = 'count111' 
-- Equation name is 'count111', location is LC032, type is buried.
count111 = TFFE( _EQ011, GLOBAL( clk), !set,  VCC,  VCC);
  _EQ011 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17 & !count18 & !count19 & !count110 & 
             !count116
         # !count18 & !count19 & !count110 &  count116 & !_LC014;

-- Node name is ':27' = 'count112' 
-- Equation name is 'count112', location is LC010, type is buried.
count112 = DFFE( _EQ012 $  VCC, GLOBAL( clk), !set,  VCC,  VCC);
  _EQ012 =  count116 & !_LC027
         # !count116 & !_LC023;

-- Node name is ':26' = 'count113' 
-- Equation name is 'count113', location is LC009, type is buried.
count113 = DFFE( _EQ013 $  VCC, GLOBAL( clk), !set,  VCC,  VCC);
  _EQ013 =  count116 & !_LC026
         # !count116 & !_LC022;

-- Node name is ':25' = 'count114' 
-- Equation name is 'count114', location is LC016, type is buried.
count114 = DFFE( _EQ014 $  VCC, GLOBAL( clk), !set,  VCC,  VCC);
  _EQ014 =  count116 & !_LC025
         # !count116 & !_LC020;

-- Node name is ':24' = 'count115' 
-- Equation name is 'count115', location is LC011, type is buried.
count115 = DFFE( _EQ015 $  VCC, GLOBAL( clk), !set,  VCC,  VCC);
  _EQ015 =  count116 & !_LC021
         # !count116 & !_LC019;

-- Node name is ':23' = 'count116' 
-- Equation name is 'count116', location is LC017, type is buried.
count116 = DFFE( _EQ016 $  VCC, GLOBAL( clk), !set,  VCC,  VCC);
  _EQ016 =  count116 &  _X001
         # !count116 & !_LC024;
  _X001  = EXP(!count18 & !count19 & !count110 & !count111 & !count112 & 
             !count113 & !count114 & !count115 & !_LC014);

-- Node name is 'square' = 'square_a' 
-- Equation name is 'square', location is LC018, type is output.
 square  = DFFE( _EQ017 $ !count116, GLOBAL( clk),  VCC,  VCC, !set);
  _EQ017 =  count115 & !count116;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried 
_LC013   = LCELL( count15 $  _EQ018);
  _EQ018 = !count10 & !count11 & !count12 & !count13 & !count14;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried 
_LC012   = LCELL( count16 $  _EQ019);
  _EQ019 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried 
_LC028   = LCELL( count17 $  _EQ020);
  _EQ020 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder1|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( _EQ021 $  GND);
  _EQ021 =  count112 &  count113 &  count114 &  count115 &  _X002
         #  count112 &  count113 &  count114 &  count115 &  _X003;
  _X002  = EXP(!count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17);
  _X003  = EXP(!count18 & !count19 & !count110 & !count111);

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL(!count112 $  _EQ022);
  _EQ022 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17 & !count18 & !count19 & !count110 & 
             !count111;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( _EQ023 $ !count113);
  _EQ023 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17 & !count18 & !count19 & !count110 & 
             !count111
         # !count112;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( _EQ024 $ !count114);
  _EQ024 = !count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17 & !count18 & !count19 & !count110 & 
             !count111
         # !count112
         # !count113;

-- Node name is '|LPM_ADD_SUB:528|addcore:adder|addcore:adder1|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried 
_LC019   = LCELL( _EQ025 $  count115);
  _EQ025 =  count112 &  count113 &  count114 &  _X003
         #  count112 &  count113 &  count114 &  _X002;
  _X003  = EXP(!count18 & !count19 & !count110 & !count111);
  _X002  = EXP(!count10 & !count11 & !count12 & !count13 & !count14 & !count15 & 
             !count16 & !count17);

-- Node name is '|LPM_ADD_SUB:614|addcore:adder|addcore:adder0|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC014', type is buried 
_LC014   = LCELL( count17 $ !count17);

-- Node name is '|LPM_ADD_SUB:614|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( count112 $  _EQ026);
  _EQ026 = !count18 & !count19 & !count110 & !count111 & !_LC014;

-- Node name is '|LPM_ADD_SUB:614|addcore:adder|addcore:adder1|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( count113 $  _EQ027);
  _EQ027 = !count18 & !count19 & !count110 & !count111 & !count112 & !_LC014;

-- Node name is '|LPM_ADD_SUB:614|addcore:adder|addcore:adder1|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( count114 $  _EQ028);
  _EQ028 = !count18 & !count19 & !count110 & !count111 & !count112 & 
             !count113 & !_LC014;

-- Node name is '|LPM_ADD_SUB:614|addcore:adder|addcore:adder1|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried 
_LC021   = LCELL( count115 $  _EQ029);
  _EQ029 = !count18 & !count19 & !count110 & !count111 & !count112 & 
             !count113 & !count114 & !_LC014;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information    d:\software\max+plus ii\xr-2206\fangbo\9-21\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,829K