📄 token_tb.vhd
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Library IEEE;
USE IEEE.std_logic_1164.all;
Entity TOKEN_TB IS
End TOKEN_TB;
Architecture behavior of TOKEN_TB is
component TOKEN
Port( CLK: in std_logic;
RST: in std_logic;
DATA: in std_logic_vector(7 downto 0);
CS: in std_logic;
A0: in std_logic;
WR: in std_logic;
READY: in std_logic;
REQ: out std_logic;
BUSY: out std_logic;
D_OUT: out std_logic;
TOKEN_IN: in std_logic;
TOKEN_OUT: out std_logic);
end component;
signal CLK: std_logic;
signal RST: std_logic;
signal DATA: std_logic_vector(7 downto 0);
signal CS: std_logic;
signal A0: std_logic;
signal WR: std_logic;
signal READY: std_logic;
signal REQ: std_logic;
signal BUSY: std_logic;
signal D_OUT: std_logic;
signal TOKEN_IN: std_logic;
signal TOKEN_OUT: std_logic;
constant T_cycle : time := 1 us;
begin
u1: TOKEN
port map ( CLK => CLK,
RST => RST,
DATA => DATA,
CS => CS,
A0 => A0,
WR => WR,
READY => READY,
REQ => REQ,
BUSY => BUSY,
D_OUT => D_OUT,
TOKEN_IN => TOKEN_IN,
TOKEN_OUT=> TOKEN_OUT) ;
Process
Begin
CLK<='1';
wait for T_cycle/2;
CLK<='0';
wait for T_cycle/2;
End process;
process
procedure RSTPRO is
begin
RST<='0';
wait for T_cycle*2;
wait for T_cycle/20;
RST<='1';
wait for T_cycle*2;
end ;
procedure R1R2PRO is
begin
CS<='0';
WR<='0';
A0<='0';
DATA<=X"44";
wait for T_cycle;
CS<='1';
WR<='1';
wait for T_cycle;
CS<='0';
WR<='0';
A0<='1';
DATA<=X"55";
wait for T_cycle;
CS<='1';
WR<='1';
wait for T_cycle;
end ;
procedure TOKEN_INPRO is
begin
wait for T_cycle*2;
TOKEN_IN<='1';
wait for T_cycle*2;
wait for T_cycle/2;
TOKEN_IN<='0';
wait for T_cycle/2;
end ;
procedure DATAPRO is
begin
CS<='0';
WR<='0';
READY<='1';
DATA<=X"01";
wait for T_cycle;
CS<='1';
WR<='1';
READY<='0';
wait for T_cycle*2;
CS<='0';
WR<='0';
READY<='1';
DATA<=X"02";
wait for T_cycle;
CS<='1';
WR<='1';
READY<='0';
wait for T_cycle*2;
CS<='0';
WR<='0';
READY<='1';
DATA<=X"03";
wait for T_cycle;
CS<='1';
WR<='1';
READY<='0';
wait for T_cycle*2;
CS<='0';
WR<='0';
READY<='1';
DATA<=X"04";
wait for T_cycle;
CS<='1';
WR<='1';
READY<='0';
wait for T_cycle*2;
CS<='0';
WR<='0';
READY<='1';
DATA<=X"05";
wait for T_cycle;
CS<='1';
WR<='1';
READY<='0';
wait for T_cycle*2;
CS<='0';
WR<='0';
READY<='1';
DATA<=X"06";
wait for T_cycle;
CS<='1';
WR<='1';
READY<='0';
wait for T_cycle*60;
end ;
begin
RSTPRO;
R1R2PRO;
TOKEN_INPRO;
DATAPRO;
end process;
End behavior;
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