token.vhd

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节

Library IEEE;
USE IEEE.std_logic_1164.all; 
USE IEEE.STD_LOGIC_UNSIGNED.all;

Entity TOKEN IS
Port( CLK:   in std_logic; 
      RST:   in std_logic;
      DATA:  in std_logic_vector(7 downto 0);
      CS:    in std_logic;
      A0:    in std_logic;
      WR:    in std_logic;
      READY: in std_logic;
      REQ:   out std_logic;
      BUSY:  out std_logic;
      D_OUT: out std_logic;
      TOKEN_IN: in std_logic;
      TOKEN_OUT: out std_logic);   
End TOKEN;

Architecture rtl of TOKEN  is 
  Type STATE is(FREE,WAIT,R2TRAN,R1TRAN,R1TRAN,DATATRAN,CHECKTRAN);  
  signal C_STATE, N_STATE: STATE;

  signal BIT_8CNT:  std_logic_vector(2 downto 0);
  signal BYTE_4CNT: std_logic_vector(1 downto 0);
  signal R2:        std_logic_vector(7 downto 0);
  signal R1:        std_logic_vector(7 downto 0);
  signal DATA_0REG: std_logic_vector(7 downto 0);
  signal DATA_1REG: std_logic_vector(7 downto 0);
  signal DATA_2REG: std_logic_vector(7 downto 0);
  signal DATA_3REG: std_logic_vector(7 downto 0);
  signal DATA_VAD:  std_logic_vector(3 downto 0);
  signal CHECK_REG: std_logic_vector(7 downto 0);
  signal CHECK_REG_IN: std_logic;
  signal SHIFT_REG: std_logic_vector(7 downto 0);  
  signal R2_WR_REG: std_logic;
  signal REQ_FIRST: std_logic;
  signal TOKEN_IN_REG: std_logic;

  
     
 
begin  	  

 ----Generate the C_STATE
 
 D_OUT<=SHIFT_REG(7);
 
Process(CLK,RST)	   	                 
Begin
    if(RST='0') then 
        C_STATE<=FREE;	  
    if(CLK'event and CLK='1' )then 
        C_STATE<=N_state;
    end if;	 
End process; 	


 ----Generate the N_STATE
Process(C_STATE,R2_WR,TOKEN_IN,BIT_8CNT,BYTE_4CNT)			     
Begin	 
case C_STATE is
    when FREE=>
        if (R2_WR='1') then	 
	    N_STATE<=WAIT; 
	else 
	    N_STATE<=FREE;
	end if;
    when WAIT=>
        if (TOKEN_IN='1') then	
	    N_STATE<=R2TRAN;   
	else 
	    N_STATE<=WAIT;
	end if;
    when R2TRAN=>
        if (BIT_8CNT="111") then	
	    N_STATE<=R1TRAN;   
	else 
	    N_STATE<=R2TRAN;
	end if;
    when R1TRAN=>
        if (BIT_8CNT="111") then	
	    N_STATE<=DATATRAN;   
	else 
	    N_STATE<=R1TRAN;
	end if;
    when DATATRAN=>
        if (BIT_8CNT="111" and BYTE_4CNT="11") then	
	    N_STATE<=CHECKTRAN;   
	else 
	    N_STATE<=DATATRAN;
	end if;
    when CHECKTRAN=>
        if (BIT_8CNT="111") then	
	    N_STATE<=FREE;  
	else 
	    N_STATE<=CHECKTRAN;
	end if;  
end case; 
end process;
 
 ----Generate the BIT_8CNT.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' )then 
        if(C_STATE=WAIT and TOKEN_IN='1') then
            BIT_8CNT<="000";
        else
            BIT_8CNT<=BIT_8CNT + '1';
        end if;
    end if;	 
End process; 

----Generate the BYTE_4CNT.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' )then 
        if(C_STATE=R1TRAN and BIT_8CNT="111") then
            BYTE_4CNT<="00";
        else
            BYTE_4CNT<=BYTE_4CNT + '1';
        end if;
    end if;	 
End process; 


----Generate the R1.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        R1<="11111111";
    if(CLK'event and CLK='1' )then 
        if(C_STATE=FREE and CS='0' and WR='0' and A0='0') then
            R1<=DATA;
        end if;
    end if;	 
End process; 


----Generate the R2.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        R2<="11111111";
    if(CLK'event and CLK='1' )then 
        if(C_STATE=FREE and CS='0' and WR='0' and A0='1') then
            R2<=DATA;
        end if;
    end if;	 
End process; 

----Generate the R2_WR_REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        R2_WR_REG<='0';
    if(CLK'event and CLK='1' )then 
        if(C_STATE=FREE and CS='0' and WR='0' and A0='1') then
            R2_WR_REG<='1';
        else 
            R2_WR_REG<='0';
        end if;
    end if;	 
End process;


----Generate the REQ.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        REQ<='0';
    if(CLK'event and CLK='1' )then 
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then
            if(DATA_VAD="0000" or DATA_VAD="0001" or DATA_VAD="0011" or DATA_VAD="0111") then 
               if(REQ='0') then 
                   REQ<='1';
               else
                   if(REQ_FIRST='1') then 
                       REQ<='1';
                   else
                       REQ<='0';
                   end if;       
               end if;
            end if;
        else
            REQ<='0';
        end if;
    end if;	 
End process;

----Generate the REQ_FIRST.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        REQ_FIRST<='0';
    if(CLK'event and CLK='1' )then 
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then
            if(DATA_VAD="0000" or DATA_VAD="0001" or DATA_VAD="0011" or DATA_VAD="0111") then 
               if(REQ='0') then 
                   REQ_FIRST<='1';
               else
                   REQ_FIRST<='0';
               end if;
            else 
               REQ_FIRST<='0';
            end if;
        else 
            REQ_FIRST<='0';
        end if;
    end if;	 
End process;


----Generate the DATA_VAD.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        DATA_VAD<="0000";
    if(CLK'event and CLK='1' )then 
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then
            if(CS='0' and WR='0' and READY='1') then
                if(DATA_VAD="0000") then 
                    DATA_VAD<="0001";
                elsif(DATA_VAD="0001") then 
                    DATA_VAD<="0011";
                elsif(DATA_VAD="0011") then 
                    DATA_VAD<="0111";
                elsif(DATA_VAD="0111") then 
                    DATA_VAD<="1111"; 
                end if;
            else
                DATA_VAD<=DATA_VAD;
        else
            DATA_VAD<="0000";
        end if;
    end if;	 
End process;

----Generate the DATA_0REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        DATA_0REG<="11111111";
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then 
            if(CS='0' and WR='0' and READY='1') then
                if(DATA_VAD='0000') then 
                    DATA_0REG<=DATA;
                else
                    DATA_0REG<=DATA_0REG;
                end if;
            else
                DATA_0REG<=DATA_0REG;
            end if;
        else
            DATA_0REG<=DATA_0REG;
        end if;
    end if;                             
End process;

----Generate the DATA_1REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        DATA_1REG<="11111111";
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then 
            if(CS='0' and WR='0' and READY='1') then
                if(DATA_VAD='0001') then 
                    DATA_1REG<=DATA;
                else
                    DATA_1REG<=DATA_1REG;
                end if;
            else
                DATA_1REG<=DATA_1REG;
            end if;
        else
            DATA_1REG<=DATA_1REG;
        end if;
    end if;                             
End process;


----Generate the DATA_2REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        DATA_2REG<="11111111";
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then 
            if(CS='0' and WR='0' and READY='1') then
                if(DATA_VAD='0011') then 
                    DATA_2REG<=DATA;
                else
                    DATA_2REG<=DATA_2REG;
                end if;
            else
                DATA_2REG<=DATA_2REG;
            end if;
        else
            DATA_2REG<=DATA_2REG;
        end if;
    end if;                             
End process;


----Generate the DATA_3REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        DATA_3REG<="11111111";
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=WAIT or C_STATE=R2TRAN or C_STATE=R1TRAN or C_STATE=DATATRAN)  then 
            if(CS='0' and WR='0' and READY='1') then
                if(DATA_VAD='0111') then 
                    DATA_3REG<=DATA;
                else
                    DATA_3REG<=DATA_3REG;
                end if;
            else
                DATA_3REG<=DATA_3REG;
            end if;
        else
            DATA_3REG<=DATA_3REG;
        end if;
    end if;                             
End process;


----Generate the SHIFT_REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        SHIFT_REG<="11111111";
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=WAIT and TOKEN_IN='1')  then 
            SHIFT_REG<=R2;
        elseif(C_STATE=R2TRAN and BIT_8CNT="111") then 
            SHIFT_REG<=R1;
        elseif(C_STATE=R1TRAN and BIT_8CNT="111") then
            SHIFT_REG<=DATA_1REG;
        elseif(C_STATE=DATATRAN and BIT_8CNT="111" and BYTE="00") then
            SHIFT_REG<=DATA_2REG;
        elseif(C_STATE=DATATRAN and BIT_8CNT="111" and BYTE="01") then
            SHIFT_REG<=DATA_3REG;
        elseif(C_STATE=DATATRAN and BIT_8CNT="111" and BYTE="10") then
            SHIFT_REG<=DATA_4REG;
        elseif(C_STATE=DATATRAN and BIT_8CNT="111" and BYTE="11") then
            SHIFT_REG<=CHECH_REG;
        elseif(C_STATE=R2RAN or C_STATE=R1TRAN or C_STATE=DATATRAN or C_STATE=CHECKTRAN)
            SHIFT_REG<=SHIFT_REG(6 downto 0) & '0';
        else 
            SHIFT_REG<=SHIFT_REG;
        end if;
    end if;                             
End process;


----Generate the CHECK_REG_IN.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        CHECK_REG_IN<='1';
    else
        CHECK_REG_IN<=CHECK_REG(2) xor CHECK_REG(4) xor CHECK_REG(7) xor SHIFT_REG(7);
    end if;                             
End process;

----Generate the CHECK_REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        CHECK_REG<="00000000";
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=DATATRAN) then
            CHECK_REG<=SHIFT_REG(6 downto 0)& CHECK_REG_IN;
        else 
            SHIFT_REG<=SHIFT_REG;
        end if;
    end if;                             
End process;


----Generate the TOKEN_IN_REG.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        TOKEN_IN_REG<='0';
    elsif(CLK'event and CLK='1' ) then
        if(TOKEN_IN='1') then
            TOKEN_IN_REG<='1';
        elseif(BUSY='0') then 
            TOKEN_IN_REG<='0';
        else 
            TOKEN_IN_REG<=TOKEN_IN_REG;
        end if;
    end if;                             
End process;


----Generate the TOKEN_OUT_FIRST.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        TOKEN_OUT_FIRST<='0';
    if(CLK'event and CLK='1' )then 
        if(C_STATE=CHECKTRAN and BIT_8CNT="111")  then 
                   TOKEN_OUT<='1';
               else
                   TOKEN_OUT<='0';
               end if;
            else 
               TOKEN_OUT<='0';
            end if;
        else 
            TOKEN_OUT<='0';
        end if;
    end if;	 
End process;


----Generate the TOKEN_OUT.
Process(CLK,RST)	   	                 
Begin	  
    if(RST='0') then 
        TOKEN_OUT<='0';
    elsif(CLK'event and CLK='1' )then
        if(C_STATE=CHECKTRAN and BIT_8CNT="111") then 
            TOKEN_OUT<='1';
        else 
            if(TOKEN_OUT_FIRST='1') then 
                TOKEN_OUT<='1';
            else
                TOKEN_OUT<='0';
            end if;    
        end if;
    end if;                             
End process;

end rtl;