pcm30.vhd

SHIFT_8REG是8位的一个具有移位功能的寄存器

Library IEEE;
USE IEEE.std_logic_1164.all; 
USE IEEE.STD_LOGIC_UNSIGNED.all;

Entity PCM30 IS
Port( CLK:   in std_logic; 
      DATA:  in std_logic;
      FLOSS: out std_logic);   
End PCM30;

Architecture rtl of PCM30  is 
  Type STATE is(BIT_SH,FIRSTF_SH,SECONDF_SH,THIRDF_SH,FIRSTF_CK,SECONDF_CK,THIRDF_CK,FOUTHF_CK);  
  signal C_STATE, N_STATE: STATE;

  signal SHIFT_8REG: std_logic_vector(7 downto 0);
  signal FRAME_256CNT: std_logic_vector(7 downto 0);
  signal ODD_110BREG: std_logic_vector(2 downto 0);
  signal EVEN_9BHREG: std_logic_vector(7 downto 0);
  signal ODD_SYN: std_logic;
  signal ODD_SYN_REG: std_logic;
  signal EVEN_SYN: std_logic;
  signal EVEN_SYN_REG: std_logic;
  signal ODD_EVEN_REG: std_logic;
 
begin  	  

 ----Generate the C_STATE
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' )then 
        C_STATE<=N_state;
    end if;	 
End process; 	


 ----Generate the N_STATE
Process(C_STATE,FRAME_256CNT,ODD_EVEN_REG,ODD_SYN,ODD_SYN_REG,EVEN_SYN,EVEN_SYN_REG)			     
Begin	 
    N_STATE<=BIT_SH;
case C_STATE is
    when BIT_SH=>
        if (EVEN_SYN='1') then	 
	    N_STATE<=FIRSTF_SH; 
	else 
	    N_STATE<=BIT_SH;
	end if;
    when FIRSTF_SH=>
        if (FRAME_256CNT="00000111" and ODD_SYN='0' and EVEN_SYN='0') then	
	    N_STATE<=BIT_SH; 
	elsif(FRAME_256CNT="11111111") then
	    N_STATE<=SECONDF_SH;  
	else 
	    N_STATE<=FIRSTF_SH;
	end if;
    when SECONDF_SH=>
        if (FRAME_256CNT="00000111" and ODD_SYN='0' and EVEN_SYN='0') then	
	    N_STATE<=BIT_SH; 
	elsif(FRAME_256CNT="11111111") then
	    N_STATE<=THIRDF_SH;  
	else 
	    N_STATE<=SECONDF_SH;
	end if;
     when THIRDF_SH=>
        if (FRAME_256CNT="00000111" and ODD_SYN='0' and EVEN_SYN='0') then	
	    N_STATE<=BIT_SH; 
	elsif(FRAME_256CNT="11111111") then
	    N_STATE<=FIRSTF_CK;  
	else 
	    N_STATE<=THIRDF_SH;
	end if;
    when FIRSTF_CK=>
        if (FRAME_256CNT="11111111") then	
            if(ODD_EVEN_REG='1') then
                if (ODD_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=SECONDF_CK;
                end if;
            else                              ----ODD_EVEN_REG='0':EVEN frame check.
                if (EVEN_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=SECONDF_CK;
                end if;
            end if;
	else 
	    N_STATE<=FIRSTF_CK;
	end if;
    when SECONDF_CK=>
        if (FRAME_256CNT="11111111") then	
            if(ODD_EVEN_REG='1') then
                if (ODD_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=THIRDF_CK;
                end if;
            else                              ----ODD_EVEN_REG='0':EVEN frame check.
                if (EVEN_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=THIRDF_CK;
                end if;
            end if;
	else 
	    N_STATE<=SECONDF_CK;
	end if;
     when THIRDF_CK=>
        if (FRAME_256CNT="11111111") then	
            if(ODD_EVEN_REG='1') then
                if (ODD_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=FOUTHF_CK;
                end if;
            else                              ----ODD_EVEN_REG='0':EVEN frame check.
                if (EVEN_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=FOUTHF_CK;
                end if;
            end if;
	else 
	    N_STATE<=THIRDF_CK;
	end if;
     when FOUTHF_CK=>
        if (FRAME_256CNT="11111111") then	
            if(ODD_EVEN_REG='1') then
                if (ODD_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=BIT_SH;
                end if;
            else                              ----ODD_EVEN_REG='0':EVEN frame check.
                if (EVEN_SYN_REG='1') then 
                    N_STATE<=FIRSTF_CK;
                else
                    N_STATE<=BIT_SH;
                end if;
            end if;
	else 
	    N_STATE<=FOUTHF_CK;
	end if;
end case; 
end process;
 
 ----Generate the FRAME_256CNT.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' )then 
        if(C_STATE=BIT_SH and EVEN_SYN='1') then
            FRAME_256CNT<="00000000";
        else
            FRAME_256CNT<=FRAME_256CNT+'1';
        end if;
    end if;	 
End process; 

 ----Generate the SHIFT_8REG.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' )then 
        SHIFT_8REG<=SHIFT_8REG(6 downto 0)&DATA;
    end if;	 
End process; 	

----Generate the ODD_110BREG.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' ) then 
        ODD_110BREG<="110";
    end if;	 
End process;

----Generate the EVEN_9BHREG.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1' ) then 
        EVEN_9BHREG<="10011011";
    end if;	 
End process;

----Generate the ODD_SYN.
Process(FRAME_256CNT,SHIFT_8REG)	   	                 
Begin	  
    if(FRAME_256CNT="00000111" and SHIFT_8REG(7 downto 5)=ODD_110BREG )then 
        ODD_SYN<='1';
    else
        ODD_SYN<='0';
    end if;	 
End process;


----Generate the ODD_SYN_REG.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1') then 
        if(FRAME_256CNT="11111111") then
            ODD_SYN_REG<='0';                      
        elsif((C_STATE=FIRSTF_CK or C_STATE=SECONDF_CK or C_STATE=THIRDF_CK or C_STATE=FOUTHF_CK or C_STATE=FIRSTF_SH or C_STATE=SECONDF_SH or C_STATE=THIRDF_SH) and FRAME_256CNT="000000111") then
            ODD_SYN_REG<=ODD_SYN;
        end if;
    end if;	 
End process;

----Generate the EVEN_SYN.
Process(FRAME_256CNT,SHIFT_8REG)	   	                 
Begin	 
    if(C_STATE=BIT_SH) then 
        if(SHIFT_8REG(7 downto 0)=EVEN_9BHREG) then
            EVEN_SYN<='1';
        else 
            EVEN_SYN<='0';
        end if;
    else
        if(FRAME_256CNT="00000111" and SHIFT_8REG(7 downto 0)=EVEN_9BHREG )then 
            EVEN_SYN<='1';
        else
            EVEN_SYN<='0';
        end if;
    end if;	 
End process;


----Generate the EVEN_SYN_REG.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1') then 
        if(FRAME_256CNT="11111111") then
            EVEN_SYN_REG<='0';
        elsif((C_STATE=FIRSTF_CK or C_STATE=SECONDF_CK or C_STATE=THIRDF_CK or C_STATE=FOUTHF_CK or C_STATE=FIRSTF_SH or C_STATE=SECONDF_SH or C_STATE=THIRDF_SH) and FRAME_256CNT="000000111") then
            EVEN_SYN_REG<=EVEN_SYN;
        end if;
    end if;	 
End process;


----Generate the ODD_EVEN_REG.
Process(CLK)	   	                 
Begin	  
    if(CLK'event and CLK='1') then 
        if(C_STATE=FIRSTF_SH and FRAME_256CNT="00000111" ) then
            if (ODD_SYN='1') then	
                ODD_EVEN_REG<='1';
            elsif(EVEN_SYN='1') then
                ODD_EVEN_REG<='0';
            end if;
        elsif((C_STATE=FIRSTF_CK or C_STATE=SECONDF_CK or C_STATE=THIRDF_CK or C_STATE=FOUTHF_CK  or C_STATE=FIRSTF_SH or C_STATE=SECONDF_SH or C_STATE=THIRDF_SH) and FRAME_256CNT="11111111") then
            if(ODD_EVEN_REG='1') then 
                ODD_EVEN_REG<='0';
            elsif(ODD_EVEN_REG='0') then
                ODD_EVEN_REG<='1';
            end if;
        end if;
    end if;	 
End process;	  


----Generate the FLOSS.
Process(CLK)	   	                 
Begin	  
    if(C_STATE=FIRSTF_CK or C_STATE=SECONDF_CK or C_STATE=THIRDF_CK or C_STATE=FOUTHF_CK) then 
        FLOSS<='1';
    else
        FLOSS<='0';
    end if;	 
End process;	

end rtl;