复件 ssdt_tb.vhd

来自「同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。」· VHDL 代码 · 共 139 行

Library IEEE;
USE IEEE.std_logic_1164.all; 


Entity SSDT_TB IS
End SSDT_TB;

Architecture behavior of SSDT_TB  is 



component SSDT
Port( FS:   std_logic;     
      RST:  std_logic;              
      CS:   std_logic;  
      CLK2M:std_logic; 
      WR:   std_logic;
      RD:   std_logic;	 
      D:    std_logic_vector(7 downto 0);
      TXD : std_logic;
      A0  : std_logic);
end component;

signal FS: std_logic;     
signal RST:  std_logic;              
signal CS: std_logic;  
signal CLK2M: std_logic; 
signal WR: std_logic;
signal RD: std_logic;	 
signal D:  std_logic_vector(7 downto 0);
signal TXD : std_logic;
signal A0  : std_logic;

signal cnt4: std_logic_vector(1 downto 0);

constant T_cycle : time := 488 ns;
constant FS_cycle : time := 124756 ns;

begin
u1: SSDT 
    port map 
        (FS=>FS,
         RST=>RST,
         CS=>CS,
         CLK2M=>CLK2M,
         WR=>WR,
         RD=>RD,
         D=>D,
         TXD=>TXD,
         A0=>A0);

Process	   	                    --CLK2M;
Begin	  
    CLK2M<='1';
    wait for T_cycle/2;
    CLK2M<='0';
    wait for T_cycle/2;
End process; 	


process
begin  
    rst <= '0';
    wait for T_cycle*2; 
    rst <= '1';	
    wait;
end process;

  
process
begin
    FS<='1';
    wait for  T_cycle*5;
    
    FS<='0';
    wait for  T_cycle/2;    
    FS<='1';
    wait for  FS_cycle;
    wait for  T_cycle/2;
    
    FS<='0';
    wait for  T_cycle/2;    
    FS<='1';
    wait for  FS_cycle;
    wait for  T_cycle/2;
    
    FS<='0';
    wait for  T_cycle/2;
    FS<='1';
    wait for  FS_cycle;
    wait for  T_cycle/2;
    
    FS<='0';
    wait for  T_cycle/2;
    wait for  FS_cycle;
end process;	

process
begin  
    WR<='0';
    RD<='1';
    wait for T_cycle;
    WR<='1';
    RD<='0';
    wait for T_cycle;    
end process;

process
begin 
    CS<='0';
    wait;
end process;

process
begin 
    A0<='0';
    wait;
end process;


process(RST,FS,RD,D,cnt4)
begin  
    if(RST='0') then 
        D<="01001111";
    end if;      
    if(FS='0') then 
        cnt4<="00";
    elsif(RD='0'and D="00000000" and cnt4="00") then  
        D<="01011100";  
    elsif(RD='0'and D="00000000" and cnt4="01") then  
        D<="00011111";  
    elsif(RD='0'and D="00000000" and cnt4="10") then  
        D<="00111101";     
    end if; 
end process;


End behavior;