ssdt_tb.vhd

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节

Library IEEE;
USE IEEE.std_logic_1164.all; 

Entity SSDT_TB IS
End SSDT_TB;

Architecture behavior of SSDT_TB  is 
component SSDT
Port( CLK2M: in std_logic; 
      FS:   in std_logic;     
      RST:  in std_logic;              
      CS:   in std_logic;
      WR:   in std_logic;
      RD:   in std_logic;	 
      A0:   in std_logic;
      D_IN: in std_logic_vector(7 downto 0);
      D_OUT:out std_logic_vector(7 downto 0);
      TXD : out std_logic);
end component;

signal FS: std_logic;     
signal RST:  std_logic;              
signal CS: std_logic;  
signal CLK2M: std_logic; 
signal WR: std_logic;
signal RD: std_logic;	 
signal D_IN:  std_logic_vector(7 downto 0);
signal D_OUT: std_logic_vector(7 downto 0);

signal TXD : std_logic;
signal A0  : std_logic;

constant T_cycle : time := 488 ns;
constant FS_cycle : time := 124928 ns;

begin
u1: SSDT 
    port map 
        (FS=>FS,
         RST=>RST,
         CS=>CS,
         CLK2M=>CLK2M,
         WR=>WR,
         RD=>RD,
         D_IN=>D_IN,
         D_OUT=>D_OUT,
         TXD=>TXD,
         A0=>A0);

Process	   	                    --CLK2M;
Begin	  
    CLK2M<='1';
    wait for T_cycle/2;
    CLK2M<='0';
    wait for T_cycle/2;
End process; 	


process
begin  
    rst <= '0';
    wait for T_cycle*2; 
    rst <= '1';	
    wait;
end process;

  
process
begin
    FS<='1';
    wait for  T_cycle*3;
    wait for  (T_cycle*3)/4;
    
    FS<='0';
    wait for  T_cycle/2;    
    FS<='1';
    wait for  FS_cycle-T_cycle/2;
    
    
    FS<='0';
    wait for  T_cycle/2;    
    FS<='1';
    wait for  FS_cycle-T_cycle/2;
    
    FS<='0';
    wait for  T_cycle/2;
    FS<='1';
    wait for  FS_cycle-T_cycle/2;
    
    FS<='0';
    wait for  T_cycle/2;
    wait;
end process;	

process
begin  
    WR<='0';  
    RD<='0';
    wait;
end process;

process
begin 
    A0<='0';
    wait;
end process;

process
begin 
    CS<='0';
    wait;
end process;

process
begin   
        D_IN<="01111110";        --1 insert 0   8
        wait for T_cycle*3; 
        D_IN<="11011111";        --2 insert 0
        wait for T_cycle*5;
        D_IN<="01010110";
        wait for T_cycle*2;
        D_IN<="01111101";        --3 insert 0
        wait for T_cycle*8;
        D_IN<="01011110";        --4  insert 0
        wait for T_cycle*9;
        D_IN<="01111010";        --5
        wait for T_cycle*6;    
        D_IN<="11111111";
        wait for T_cycle*3;   
        D_IN<="10011111";        --6 7
        wait for T_cycle*10;
end process;


End behavior;