ssdt_tbz.vhd

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节

library ieee;

use ieee.std_logic_1164.all;


entity sync_data_sender_tb is
end sync_data_sender_tb;

architecture TB_ARCHITECTURE of sync_data_sender_tb is

 component SSDT
    port(
     clk:in std_logic;
     rst:in std_logic;
     fs:in std_logic;
     cs_n:in std_logic;
     a0:in std_logic;
     wr_n:in std_logic;
     rd_n:in std_logic;
     data_in:in std_logic_vector(7 downto 0);
     data_out:out std_logic_vector(7 downto 0);
     td:out std_logic);    
 end component;
 
 signal clk: std_logic;
 signal rst: std_logic;
 signal fs: std_logic;
 signal cs_n: std_logic;
 signal a0: std_logic;
 signal wr_n: std_logic;
 signal rd_n: std_logic;
 signal data_in: std_logic_vector(7 downto 0);
 signal data_out: std_logic_vector(7 downto 0);
 signal td: std_logic;
 -----------------------------------------------
 constant clk_period : time := 488 ns;
 constant fs_period  : time := 124928 ns;
 
 begin
 
 u1 : SSDT							  
        PORT MAP(								  
            clk => clk,
     				rst => rst,
     				fs => fs,
     				cs_n => cs_n,
     				a0 => a0,
    				wr_n => wr_n,
     				rd_n => rd_n,
     				data_in => data_in,
     				data_out => data_out,
     				td => td
        );
        
        
        
process
begin
	clk<='1';
	wait for clk_period/2;
	clk<='0';
	wait for clk_period/2;
end process;

process
begin  
	rst <= '1';
	wait for clk_period*3; 
	rst <= '0';	
	wait;
end process;


process
begin
	fs<='1';
	wait for  fs_period;
	wait for  (clk_period*3)/4;
	fs<='0';
	wait for  clk_period/2;
	
	fs<='1';
	wait for  fs_period;
	wait for  clk_period/2;
	fs<='0';
	wait for  clk_period/2;
	
	fs<='1';
	wait for  fs_period;
	wait for  clk_period/4;
	fs<='0';
	wait for  clk_period/2;
	
	fs<='1';
	wait for  fs_period;
	fs<='0';
	wait for  clk_period/2;
end process;	


process


procedure RESET	is
begin
	cs_n<='1';
	a0<='0';
	wr_n<='1';
	rd_n<='1';
	data_in<="00000000";
	wait for clk_period;
end;

procedure READ_THR	is
begin
	cs_n<='0';
	a0<='0';
	wait for clk_period*3;
	wr_n<='1';
	rd_n<='0';
	wait for clk_period*3;
	wr_n<='1';
	rd_n<='1';
	wait for clk_period*3;
end;


procedure WRITE_THR(data:std_logic_vector(7 downto 0))	is
begin
	cs_n<='0';
	a0<='0';
	data_in<=data;
	wait for clk_period*3;
	wr_n<='0';
	rd_n<='1';
	wait for clk_period*3;
	wr_n<='1';
	rd_n<='1';
	wait for clk_period*3;
end;

begin

RESET;

wait for clk_period;
READ_THR;

WRITE_THR(X"7f");
WRITE_THR(X"5a");
WRITE_THR(X"7f");
WRITE_THR(X"5a");

wait for clk_period*3;
READ_THR;

wait;


end process;
	
	
	



















end TB_ARCHITECTURE;