calcu_synthesis.vhd

本程序实现两个整数平方和相加并且输出结果

    port map (
      I0 => sa(0),
      I1 => sb(0),
      LO => N4
    );
  calcucy : MUXCY
    port map (
      CI => N1,
      DI => sa(0),
      S => N4,
      O => calcu_cyo
    );
  calcu_n0007_1_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(1),
      I1 => sb(1),
      LO => N5
    );
  calcu_n0007_1_cy : MUXCY
    port map (
      CI => calcu_cyo,
      DI => sa(1),
      S => N5,
      O => calcu_n0007_1_cyo
    );
  calcu_n0007_1_xor : XORCY
    port map (
      CI => calcu_cyo,
      LI => N5,
      O => Q_n0007(1)
    );
  calcu_n0007_2_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(2),
      I1 => sb(2),
      LO => N6
    );
  calcu_n0007_2_cy : MUXCY
    port map (
      CI => calcu_n0007_1_cyo,
      DI => sa(2),
      S => N6,
      O => calcu_n0007_2_cyo
    );
  calcu_n0007_2_xor : XORCY
    port map (
      CI => calcu_n0007_1_cyo,
      LI => N6,
      O => Q_n0007(2)
    );
  calcu_n0007_3_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(3),
      I1 => sb(3),
      LO => N7
    );
  calcu_n0007_3_cy : MUXCY
    port map (
      CI => calcu_n0007_2_cyo,
      DI => sa(3),
      S => N7,
      O => calcu_n0007_3_cyo
    );
  calcu_n0007_3_xor : XORCY
    port map (
      CI => calcu_n0007_2_cyo,
      LI => N7,
      O => Q_n0007(3)
    );
  calcu_n0007_4_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(4),
      I1 => sb(4),
      LO => N8
    );
  calcu_n0007_4_cy : MUXCY
    port map (
      CI => calcu_n0007_3_cyo,
      DI => sa(4),
      S => N8,
      O => calcu_n0007_4_cyo
    );
  calcu_n0007_4_xor : XORCY
    port map (
      CI => calcu_n0007_3_cyo,
      LI => N8,
      O => Q_n0007(4)
    );
  calcu_n0007_5_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(5),
      I1 => sb(5),
      LO => N9
    );
  calcu_n0007_5_cy : MUXCY
    port map (
      CI => calcu_n0007_4_cyo,
      DI => sa(5),
      S => N9,
      O => calcu_n0007_5_cyo
    );
  calcu_n0007_5_xor : XORCY
    port map (
      CI => calcu_n0007_4_cyo,
      LI => N9,
      O => Q_n0007(5)
    );
  calcu_n0007_6_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(6),
      I1 => sb(6),
      LO => N10
    );
  calcu_n0007_6_cy : MUXCY
    port map (
      CI => calcu_n0007_5_cyo,
      DI => sa(6),
      S => N10,
      O => calcu_n0007_6_cyo
    );
  calcu_n0007_6_xor : XORCY
    port map (
      CI => calcu_n0007_5_cyo,
      LI => N10,
      O => Q_n0007(6)
    );
  calcu_n0007_7_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sa(7),
      I1 => sb(7),
      LO => N11
    );
  calcu_n0007_7_cy : MUXCY
    port map (
      CI => calcu_n0007_6_cyo,
      DI => sa(7),
      S => N11,
      O => Q_n0000(8)
    );
  calcu_stmp_n0000_0_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => sc(0),
      I1 => stmp(0),
      LO => N12
    );
  calcu_stmp_n0000_0_cy : MUXCY
    port map (
      CI => N1,
      DI => stmp(0),
      S => N12,
      O => calcu_stmp_n0000_0_cyo
    );
  sum_0_OBUF : OBUF
    port map (
      I => stmp(0),
      O => sum(0)
    );
  calcu_stmp_n0000_1_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(1),
      I1 => sc(1),
      LO => N13
    );
  calcu_stmp_n0000_1_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_0_cyo,
      DI => stmp(1),
      S => N13,
      O => calcu_stmp_n0000_1_cyo
    );
  calcu_stmp_n0000_1_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_0_cyo,
      LI => N13,
      O => stmp_n0000(1)
    );
  calcu_stmp_n0000_2_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(2),
      I1 => sc(2),
      LO => N14
    );
  calcu_stmp_n0000_2_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_1_cyo,
      DI => stmp(2),
      S => N14,
      O => calcu_stmp_n0000_2_cyo
    );
  calcu_stmp_n0000_2_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_1_cyo,
      LI => N14,
      O => stmp_n0000(2)
    );
  calcu_stmp_n0000_3_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(3),
      I1 => sc(3),
      LO => N15
    );
  calcu_stmp_n0000_3_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_2_cyo,
      DI => stmp(3),
      S => N15,
      O => calcu_stmp_n0000_3_cyo
    );
  calcu_stmp_n0000_3_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_2_cyo,
      LI => N15,
      O => stmp_n0000(3)
    );
  calcu_stmp_n0000_4_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(4),
      I1 => sc(4),
      LO => N16
    );
  calcu_stmp_n0000_4_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_3_cyo,
      DI => stmp(4),
      S => N16,
      O => calcu_stmp_n0000_4_cyo
    );
  calcu_stmp_n0000_4_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_3_cyo,
      LI => N16,
      O => stmp_n0000(4)
    );
  calcu_stmp_n0000_5_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(5),
      I1 => sc(5),
      LO => N17
    );
  calcu_stmp_n0000_5_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_4_cyo,
      DI => stmp(5),
      S => N17,
      O => calcu_stmp_n0000_5_cyo
    );
  calcu_stmp_n0000_5_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_4_cyo,
      LI => N17,
      O => stmp_n0000(5)
    );
  calcu_stmp_n0000_6_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(6),
      I1 => sc(6),
      LO => N18
    );
  calcu_stmp_n0000_6_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_5_cyo,
      DI => stmp(6),
      S => N18,
      O => calcu_stmp_n0000_6_cyo
    );
  calcu_stmp_n0000_6_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_5_cyo,
      LI => N18,
      O => stmp_n0000(6)
    );
  calcu_stmp_n0000_7_lut : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => stmp(7),
      I1 => sc(7),
      LO => N19
    );
  calcu_stmp_n0000_7_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_6_cyo,
      DI => stmp(7),
      S => N19,
      O => calcu_stmp_n0000_7_cyo
    );
  calcu_stmp_n0000_7_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_6_cyo,
      LI => N19,
      O => stmp_n0000(7)
    );
  calcu_stmp_n0000_8_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_7_cyo,
      DI => N1,
      S => stmp_8_rt,
      O => calcu_stmp_n0000_8_cyo
    );
  calcu_stmp_n0000_8_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_7_cyo,
      LI => stmp_8_rt,
      O => stmp_n0000(8)
    );
  calcu_stmp_n0000_9_cy : MUXCY
    port map (
      CI => calcu_stmp_n0000_8_cyo,
      DI => N1,
      S => stmp_9_rt,
      O => calcu_stmp_n0000_9_cyo
    );
  calcu_stmp_n0000_9_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_8_cyo,
      LI => stmp_9_rt,
      O => stmp_n0000(9)
    );
  Q_n0005_2_1_SW0 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => uut1_count(0),
      I1 => c_reg(2),
      I2 => s_reg(2),
      LO => N251
    );
  stmp_10_rt_0 : LUT1
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => stmp(10),
      O => stmp_10_rt
    );
  stmp_9_rt_1 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => stmp(9),
      LO => stmp_9_rt
    );
  stmp_8_rt_2 : LUT1_L
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => stmp(8),
      LO => stmp_8_rt
    );
  Q_n00151 : LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      I0 => uut1_clear,
      I1 => reset_IBUF,
      O => Q_n0015
    );
  Q_n00061 : LUT3
    generic map(
      INIT => X"10"
    )
    port map (
      I0 => uut1_count(0),
      I1 => uut1_count(1),
      I2 => uut1_count(2),
      O => Q_n0006
    );
  Q_n00031 : LUT4_L
    generic map(
      INIT => X"DFFF"
    )
    port map (
      I0 => reset_IBUF,
      I1 => uut1_count(2),
      I2 => uut1_count(1),
      I3 => uut1_count(0),
      LO => N23
    );
  Q_n00032 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => uut1_clear,
      I1 => N23,
      O => Q_n0003
    );
  Q_n00021 : LUT4_L
    generic map(
      INIT => X"FDFF"
    )
    port map (
      I0 => reset_IBUF,
      I1 => uut1_count(2),
      I2 => uut1_count(0),
      I3 => uut1_count(1),
      LO => N25
    );
  Q_n00022 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => uut1_clear,
      I1 => N25,
      O => Q_n0002
    );
  Q_n00011 : LUT4_L
    generic map(
      INIT => X"FDFF"
    )
    port map (
      I0 => reset_IBUF,
      I1 => uut1_count(2),
      I2 => uut1_count(1),
      I3 => uut1_count(0),
      LO => N27
    );
  Q_n00012 : LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      I0 => uut1_clear,
      I1 => N27,
      O => Q_n0001
    );
  sum_1_OBUF : OBUF
    port map (
      I => stmp(1),
      O => sum(1)
    );
  uut1_count2_0 : FDP
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_count2_n0001(0),
      PRE => uut1_clear_N0,
      C => uut1_sclk_307k,
      Q => uut1_count2(0)
    );
  uut1_count2_2 : FDP
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_count2_n0001(2),
      PRE => uut1_clear_N0,
      C => uut1_sclk_307k,
      Q => uut1_count2(2)
    );
  uut1_count2_1 : FDP
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_count2_n0001(1),
      PRE => uut1_clear_N0,
      C => uut1_sclk_307k,
      Q => uut1_count2(1)
    );
  uut1_count2_n0001_1_1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => uut1_count2(0),
      I1 => uut1_count2(1),
      O => uut1_count2_n0001(1)
    );
  uut1_count2_n0001_0_1_INV_0 : INV
    port map (
      I => uut1_count2(0),
      O => uut1_count2_n0001(0)
    );
  uut1_n000525 : LUT4_L
    generic map(
      INIT => X"FAF8"
    )
    port map (
      I0 => uut1_clear,
      I1 => uut1_count(1),
      I2 => CHOICE31,
      I3 => CHOICE25,
      LO => uut1_n0005
    );
  uut1_clear_N01_INV_0 : INV
    port map (
      I => reset_IBUF,
      O => uut1_clear_N0
    );
  uut1_sclk_307k_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_n0003,
      CLR => uut1_clear_N0,
      C => clk_BUFGP,
      Q => uut1_sclk_307k
    );
  uut1_count2_n0001_2_1 : LUT3
    generic map(
      INIT => X"78"
    )
    port map (
      I0 => uut1_count2(0),
      I1 => uut1_count2(1),
      I2 => uut1_count2(2),
      O => uut1_count2_n0001(2)
    );
  uut1_n0002_0_1_INV_0 : INV
    port map (
      I => uut1_count(0),
      O => uut1_n0002(0)
    );
  uut1_n00031 : LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      I0 => uut1_sclk_307k,
      I1 => uut1_count(0),
      I2 => uut1_count(1),
      I3 => uut1_count(2),
      O => uut1_n0003
    );
  uut1_count_1 : FDP
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_n0002(1),
      PRE => uut1_clear_N0,
      C => clk_BUFGP,
      Q => uut1_count(1)
    );
  uut1_count_0 : FDP
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_n0002(0),
      PRE => uut1_clear_N0,
      C => clk_BUFGP,
      Q => uut1_count(0)
    );
  uut1_n0002_2_1 : LUT3
    generic map(
      INIT => X"78"
    )
    port map (
      I0 => uut1_count(0),
      I1 => uut1_count(1),
      I2 => uut1_count(2),
      O => uut1_n0002(2)
    );
  uut1_clear_4 : FDP
    port map (
      D => uut1_n0005,
      PRE => uut1_clear_N0,
      C => clk_BUFGP,
      Q => uut1_clear
    );
  uut1_count_2 : FDP
    generic map(
      INIT => '0'
    )
    port map (
      D => uut1_n0002(2),
      PRE => uut1_clear_N0,
      C => clk_BUFGP,
      Q => uut1_count(2)
    );
  uut1_n00055 : LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      I0 => uut1_count2(1),
      I1 => uut1_count2(2),
      I2 => uut1_count2(0),
      I3 => uut1_count(2),
      O => CHOICE25
    );
  uut1_n000522 : LUT3_L
    generic map(
      INIT => X"10"
    )
    port map (
      I0 => uut1_count(1),
      I1 => uut1_count(2),
      I2 => uut1_count(0),
      LO => CHOICE31
    );
  clk_BUFGP_5 : BUFGP
    port map (
      I => clk,
      O => clk_BUFGP
    );
  reset_IBUF_6 : IBUF
    port map (
      I => reset,
      O => reset_IBUF
    );
  c_3_IBUF_7 : IBUF
    port map (
      I => c(3),
      O => c_3_IBUF
    );
  c_2_IBUF_8 : IBUF
    port map (
      I => c(2),
      O => c_2_IBUF
    );
  c_1_IBUF_9 : IBUF
    port map (
      I => c(1),
      O => c_1_IBUF
    );
  c_0_IBUF_10 : IBUF
    port map (
      I => c(0),
      O => c_0_IBUF
    );
  s_3_IBUF_11 : IBUF
    port map (
      I => s(3),
      O => s_3_IBUF
    );
  s_2_IBUF_12 : IBUF
    port map (
      I => s(2),
      O => s_2_IBUF
    );
  s_1_IBUF_13 : IBUF
    port map (
      I => s(1),
      O => s_1_IBUF
    );
  s_0_IBUF_14 : IBUF
    port map (
      I => s(0),
      O => s_0_IBUF
    );
  sum_10_OBUF : OBUF
    port map (
      I => stmp(10),
      O => sum(10)
    );
  sum_9_OBUF : OBUF
    port map (
      I => stmp(9),
      O => sum(9)
    );
  sum_8_OBUF : OBUF
    port map (
      I => stmp(8),
      O => sum(8)
    );
  sum_7_OBUF : OBUF
    port map (
      I => stmp(7),
      O => sum(7)
    );
  sum_6_OBUF : OBUF
    port map (
      I => stmp(6),
      O => sum(6)
    );
  sum_5_OBUF : OBUF
    port map (
      I => stmp(5),
      O => sum(5)
    );
  sum_4_OBUF : OBUF
    port map (
      I => stmp(4),
      O => sum(4)
    );
  sum_3_OBUF : OBUF
    port map (
      I => stmp(3),
      O => sum(3)
    );
  sum_2_OBUF : OBUF
    port map (
      I => stmp(2),
      O => sum(2)
    );

end Structure;