calcu_synthesis.vhd

本程序实现两个整数平方和相加并且输出结果

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: calcu_synthesis.vhd
-- /___/   /\     Timestamp: Wed Sep 28 22:28:11 2005
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -ar Structure -w -ofmt vhdl -sim calcu.ngc calcu_synthesis.vhd 
-- Device: xc3s50-4-pq208
-- Design Name: calcu
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity calcu is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    c : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    s : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    sum : out STD_LOGIC_VECTOR ( 10 downto 0 ) 
  );
end calcu;

architecture Structure of calcu is
  component asyn_rom_16x8
    port (
      MemEnab : in STD_LOGIC := 'X'; 
      Address : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
      Q : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  signal clk_BUFGP : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal uut1_clear : STD_LOGIC; 
  signal Q_n0001 : STD_LOGIC; 
  signal Q_n0002 : STD_LOGIC; 
  signal Q_n0003 : STD_LOGIC; 
  signal Q_n0006 : STD_LOGIC; 
  signal Q_n0013 : STD_LOGIC; 
  signal Q_n0015 : STD_LOGIC; 
  signal uut1_sclk_307k : STD_LOGIC; 
  signal c_3_IBUF : STD_LOGIC; 
  signal c_2_IBUF : STD_LOGIC; 
  signal c_1_IBUF : STD_LOGIC; 
  signal c_0_IBUF : STD_LOGIC; 
  signal s_3_IBUF : STD_LOGIC; 
  signal s_2_IBUF : STD_LOGIC; 
  signal s_1_IBUF : STD_LOGIC; 
  signal s_0_IBUF : STD_LOGIC; 
  signal stmp_10_rt : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal N1 : STD_LOGIC; 
  signal calcu_stmp_n0000_8_cyo : STD_LOGIC; 
  signal calcu_stmp_n0000_9_cyo : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal calcu_cyo : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal calcu_n0007_1_cyo : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal calcu_n0007_2_cyo : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal calcu_n0007_3_cyo : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal calcu_n0007_4_cyo : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal calcu_n0007_5_cyo : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal calcu_n0007_6_cyo : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal calcu_stmp_n0000_7_cyo : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal calcu_stmp_n0000_0_cyo : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal calcu_stmp_n0000_1_cyo : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal calcu_stmp_n0000_2_cyo : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal calcu_stmp_n0000_3_cyo : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal calcu_stmp_n0000_4_cyo : STD_LOGIC; 
  signal N17 : STD_LOGIC; 
  signal calcu_stmp_n0000_5_cyo : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal calcu_stmp_n0000_6_cyo : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal N23 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal N27 : STD_LOGIC; 
  signal N251 : STD_LOGIC; 
  signal stmp_8_rt : STD_LOGIC; 
  signal N271 : STD_LOGIC; 
  signal N29 : STD_LOGIC; 
  signal stmp_9_rt : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal uut1_n0003 : STD_LOGIC; 
  signal uut1_clear_N0 : STD_LOGIC; 
  signal uut1_n0005 : STD_LOGIC; 
  signal CHOICE25 : STD_LOGIC; 
  signal CHOICE31 : STD_LOGIC; 
  signal sc : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal so : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal sb : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal s_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal sa : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal stmp : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal uut1_count : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal si : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal c_reg : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Q_n0005 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Q_n0007 : STD_LOGIC_VECTOR ( 7 downto 1 ); 
  signal Q_n0000 : STD_LOGIC_VECTOR ( 8 downto 8 ); 
  signal stmp_n0000 : STD_LOGIC_VECTOR ( 10 downto 1 ); 
  signal uut1_n0002 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal uut1_count2_n0001 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal uut1_count2 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  Q_n0005_0_1 : LUT4_L
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => si(0),
      I1 => uut1_count(1),
      I2 => uut1_count(2),
      I3 => N31,
      LO => Q_n0005(0)
    );
  Q_n0005_0_1_SW0 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => uut1_count(0),
      I1 => c_reg(0),
      I2 => s_reg(0),
      LO => N31
    );
  Q_n00131 : LUT2
    generic map(
      INIT => X"7"
    )
    port map (
      I0 => reset_IBUF,
      I1 => uut1_clear,
      O => Q_n0013
    );
  sb_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(6),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(6)
    );
  sb_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(5),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(5)
    );
  sb_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(4),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(4)
    );
  Q_n0005_1_1 : LUT4_L
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => si(1),
      I1 => uut1_count(1),
      I2 => uut1_count(2),
      I3 => N29,
      LO => Q_n0005(1)
    );
  Q_n0005_1_1_SW0 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => uut1_count(0),
      I1 => c_reg(1),
      I2 => s_reg(1),
      LO => N29
    );
  Q_n0005_3_1 : LUT4_L
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => si(3),
      I1 => uut1_count(1),
      I2 => uut1_count(2),
      I3 => N271,
      LO => Q_n0005(3)
    );
  Q_n0005_3_1_SW0 : LUT3_L
    generic map(
      INIT => X"E4"
    )
    port map (
      I0 => uut1_count(0),
      I1 => c_reg(3),
      I2 => s_reg(3),
      LO => N271
    );
  Q_n0005_2_1 : LUT4_L
    generic map(
      INIT => X"ABA8"
    )
    port map (
      I0 => si(2),
      I1 => uut1_count(1),
      I2 => uut1_count(2),
      I3 => N251,
      LO => Q_n0005(2)
    );
  calcu_n0007_7_xor : XORCY
    port map (
      CI => calcu_n0007_6_cyo,
      LI => N11,
      O => Q_n0007(7)
    );
  stmp_9 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(9),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(9)
    );
  s_reg_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => s_3_IBUF,
      C => uut1_sclk_307k,
      Q => s_reg(3)
    );
  si_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0005(3),
      CE => Q_n0015,
      C => clk_BUFGP,
      Q => si(3)
    );
  sc_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0000(8),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(7)
    );
  uut1_n0002_1_1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => uut1_count(0),
      I1 => uut1_count(1),
      O => uut1_n0002(1)
    );
  uut2_sq16x8_tab : asyn_rom_16x8
    port map (
      MemEnab => N0,
      Address(3) => si(3),
      Address(2) => si(2),
      Address(1) => si(1),
      Address(0) => si(0),
      Q(7) => so(7),
      Q(6) => so(6),
      Q(5) => so(5),
      Q(4) => so(4),
      Q(3) => so(3),
      Q(2) => so(2),
      Q(1) => so(1),
      Q(0) => so(0)
    );
  c_reg_3 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => c_3_IBUF,
      C => uut1_sclk_307k,
      Q => c_reg(3)
    );
  sa_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(7),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(7)
    );
  sb_7 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(7),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(7)
    );
  s_reg_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => s_0_IBUF,
      C => uut1_sclk_307k,
      Q => s_reg(0)
    );
  s_reg_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => s_1_IBUF,
      C => uut1_sclk_307k,
      Q => s_reg(1)
    );
  s_reg_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => s_2_IBUF,
      C => uut1_sclk_307k,
      Q => s_reg(2)
    );
  si_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0005(0),
      CE => Q_n0015,
      C => clk_BUFGP,
      Q => si(0)
    );
  si_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0005(1),
      CE => Q_n0015,
      C => clk_BUFGP,
      Q => si(1)
    );
  si_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0005(2),
      CE => Q_n0015,
      C => clk_BUFGP,
      Q => si(2)
    );
  sc_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(1),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(0)
    );
  sc_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(2),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(1)
    );
  sc_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(3),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(2)
    );
  sc_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(4),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(3)
    );
  sc_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(5),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(4)
    );
  sc_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(6),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(5)
    );
  sc_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => Q_n0007(7),
      CE => Q_n0003,
      C => clk_BUFGP,
      Q => sc(6)
    );
  c_reg_0 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => c_0_IBUF,
      C => uut1_sclk_307k,
      Q => c_reg(0)
    );
  c_reg_1 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => c_1_IBUF,
      C => uut1_sclk_307k,
      Q => c_reg(1)
    );
  c_reg_2 : FD
    generic map(
      INIT => '0'
    )
    port map (
      D => c_2_IBUF,
      C => uut1_sclk_307k,
      Q => c_reg(2)
    );
  sa_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(0),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(0)
    );
  sa_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(1),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(1)
    );
  sa_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(2),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(2)
    );
  sa_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(3),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(3)
    );
  sa_4 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(4),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(4)
    );
  sa_5 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(5),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(5)
    );
  sa_6 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(6),
      CE => Q_n0001,
      C => clk_BUFGP,
      Q => sa(6)
    );
  sb_0 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(0),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(0)
    );
  sb_1 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(1),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(1)
    );
  sb_2 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(2),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(2)
    );
  sb_3 : FDE
    generic map(
      INIT => '0'
    )
    port map (
      D => so(3),
      CE => Q_n0002,
      C => clk_BUFGP,
      Q => sb(3)
    );
  stmp_10 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(10),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(10)
    );
  calcu_stmp_n0000_10_xor : XORCY
    port map (
      CI => calcu_stmp_n0000_9_cyo,
      LI => stmp_10_rt,
      O => stmp_n0000(10)
    );
  stmp_8 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(8),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(8)
    );
  stmp_0 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => N12,
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(0)
    );
  stmp_1 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(1),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(1)
    );
  stmp_2 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(2),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(2)
    );
  stmp_3 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(3),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(3)
    );
  stmp_4 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(4),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(4)
    );
  stmp_5 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(5),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(5)
    );
  stmp_6 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(6),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(6)
    );
  stmp_7 : FDCE
    generic map(
      INIT => '0'
    )
    port map (
      D => stmp_n0000(7),
      CE => Q_n0006,
      CLR => Q_n0013,
      C => clk_BUFGP,
      Q => stmp(7)
    );
  XST_VCC : VCC
    port map (
      P => N0
    );
  XST_GND : GND
    port map (
      G => N1
    );
  calculut : LUT2_L
    generic map(
      INIT => X"6"
    )