clk_gen_translate.vhd

本程序实现不同频率时钟的产生及其相互转化

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: clk_gen_translate.vhd
-- /___/   /\     Timestamp: Wed Sep 28 23:18:52 2005
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim clk_gen.ngd clk_gen_translate.vhd 
-- Device: 3s50pq208-4
-- Design Name: clk_gen
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity clk_gen is
  port (
    reset : in STD_LOGIC := 'X'; 
    clk_2M : in STD_LOGIC := 'X'; 
    clk_307k : out STD_LOGIC; 
    clear : out STD_LOGIC; 
    clk_count : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end clk_gen;

architecture Structure of clk_gen is
  signal sclk_307k : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal clear_OBUF : STD_LOGIC; 
  signal clk_2M_BUFGP : STD_LOGIC; 
  signal Q_n0003 : STD_LOGIC; 
  signal Q_n0005 : STD_LOGIC; 
  signal clear_N0 : STD_LOGIC; 
  signal CHOICE25 : STD_LOGIC; 
  signal CHOICE31 : STD_LOGIC; 
  signal count2_n0001_1_1_O : STD_LOGIC; 
  signal Q_n000525_O : STD_LOGIC; 
  signal count2_n0001_2_1_O : STD_LOGIC; 
  signal Q_n00031_O : STD_LOGIC; 
  signal Q_n0002_2_1_O : STD_LOGIC; 
  signal Q_n0002_1_1_O : STD_LOGIC; 
  signal Q_n000522_O : STD_LOGIC; 
  signal clk_2M_BUFGP_IBUFG : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal sclk_307k_GSR_OR : STD_LOGIC; 
  signal clear_GSR_OR : STD_LOGIC; 
  signal clk_count_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal clk_count_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal clk_307k_OBUF_GTS_TRI : STD_LOGIC; 
  signal clear_OBUF_GTS_TRI : STD_LOGIC; 
  signal clk_count_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwInverterSignal_clk_count_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_clk_count_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_clk_307k_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_clear_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_clk_count_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal count2 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal count2_n0001 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal count : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal Q_n0002 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  count2_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => count2_n0001(0),
      SET => clear_N0,
      CLK => sclk_307k,
      O => count2(0),
      CE => VCC,
      RST => GSR
    );
  clk_count_0_OBUF : X_BUF
    port map (
      I => count(0),
      O => clk_count_0_OBUF_GTS_TRI
    );
  clk_count_1_OBUF : X_BUF
    port map (
      I => count(1),
      O => clk_count_1_OBUF_GTS_TRI
    );
  count2_n0001_0_1_INV_0 : X_INV
    port map (
      I => count2(0),
      O => count2_n0001(0)
    );
  clear_N01_INV_0 : X_INV
    port map (
      I => reset_IBUF,
      O => clear_N0
    );
  sclk_307k_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0003,
      RST => sclk_307k_GSR_OR,
      CLK => clk_2M_BUFGP,
      O => sclk_307k,
      CE => VCC,
      SET => GND
    );
  Q_n0002_0_1_INV_0 : X_INV
    port map (
      I => count(0),
      O => Q_n0002(0)
    );
  count_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(1),
      SET => clear_N0,
      CLK => clk_2M_BUFGP,
      O => count(1),
      CE => VCC,
      RST => GSR
    );
  count_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(0),
      SET => clear_N0,
      CLK => clk_2M_BUFGP,
      O => count(0),
      CE => VCC,
      RST => GSR
    );
  clear_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => Q_n0005,
      SET => clear_GSR_OR,
      CLK => clk_2M_BUFGP,
      O => clear_OBUF,
      CE => VCC,
      RST => GND
    );
  count_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Q_n0002(2),
      SET => clear_N0,
      CLK => clk_2M_BUFGP,
      O => count(2),
      CE => VCC,
      RST => GSR
    );
  count2_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => count2_n0001(2),
      SET => clear_N0,
      CLK => sclk_307k,
      O => count2(2),
      CE => VCC,
      RST => GSR
    );
  count2_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => count2_n0001(1),
      SET => clear_N0,
      CLK => sclk_307k,
      O => count2(1),
      CE => VCC,
      RST => GSR
    );
  Q_n00055 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => count2(1),
      ADR1 => count2(2),
      ADR2 => count2(0),
      ADR3 => count(2),
      O => CHOICE25
    );
  reset_IBUF_2 : X_BUF
    port map (
      I => reset,
      O => reset_IBUF
    );
  clk_307k_OBUF : X_BUF
    port map (
      I => sclk_307k,
      O => clk_307k_OBUF_GTS_TRI
    );
  clear_OBUF_3 : X_BUF
    port map (
      I => clear_OBUF,
      O => clear_OBUF_GTS_TRI
    );
  clk_count_2_OBUF : X_BUF
    port map (
      I => count(2),
      O => clk_count_2_OBUF_GTS_TRI
    );
  count2_n0001_1_1_LUT2_L_BUF : X_BUF
    port map (
      I => count2_n0001_1_1_O,
      O => count2_n0001(1)
    );
  count2_n0001_1_1 : X_LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      ADR0 => count2(0),
      ADR1 => count2(1),
      O => count2_n0001_1_1_O
    );
  Q_n000525_LUT4_L_BUF : X_BUF
    port map (
      I => Q_n000525_O,
      O => Q_n0005
    );
  Q_n000525 : X_LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      ADR0 => clear_OBUF,
      ADR1 => count(1),
      ADR2 => CHOICE31,
      ADR3 => CHOICE25,
      O => Q_n000525_O
    );
  count2_n0001_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => count2_n0001_2_1_O,
      O => count2_n0001(2)
    );
  count2_n0001_2_1 : X_LUT3
    generic map(
      INIT => X"78"
    )
    port map (
      ADR0 => count2(0),
      ADR1 => count2(1),
      ADR2 => count2(2),
      O => count2_n0001_2_1_O
    );
  Q_n00031_LUT4_L_BUF : X_BUF
    port map (
      I => Q_n00031_O,
      O => Q_n0003
    );
  Q_n00031 : X_LUT4
    generic map(
      INIT => X"EA2A"
    )
    port map (
      ADR0 => sclk_307k,
      ADR1 => count(0),
      ADR2 => count(1),
      ADR3 => count(2),
      O => Q_n00031_O
    );
  Q_n0002_2_1_LUT3_L_BUF : X_BUF
    port map (
      I => Q_n0002_2_1_O,
      O => Q_n0002(2)
    );
  Q_n0002_2_1 : X_LUT3
    generic map(
      INIT => X"78"
    )
    port map (
      ADR0 => count(0),
      ADR1 => count(1),
      ADR2 => count(2),
      O => Q_n0002_2_1_O
    );
  Q_n0002_1_1_LUT2_L_BUF : X_BUF
    port map (
      I => Q_n0002_1_1_O,
      O => Q_n0002(1)
    );
  Q_n0002_1_1 : X_LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      ADR0 => count(0),
      ADR1 => count(1),
      O => Q_n0002_1_1_O
    );
  Q_n000522_LUT3_L_BUF : X_BUF
    port map (
      I => Q_n000522_O,
      O => CHOICE31
    );
  Q_n000522 : X_LUT3
    generic map(
      INIT => X"04"
    )
    port map (
      ADR0 => count(2),
      ADR1 => count(0),
      ADR2 => count(1),
      O => Q_n000522_O
    );
  clk_2M_BUFGP_BUFG : X_CKBUF
    port map (
      I => clk_2M_BUFGP_IBUFG,
      O => clk_2M_BUFGP
    );
  clk_2M_BUFGP_IBUFG_7 : X_CKBUF
    port map (
      I => clk_2M,
      O => clk_2M_BUFGP_IBUFG
    );
  sclk_307k_GSR_OR_8 : X_OR2
    port map (
      I0 => clear_N0,
      I1 => GSR,
      O => sclk_307k_GSR_OR
    );
  clear_GSR_OR_9 : X_OR2
    port map (
      I0 => clear_N0,
      I1 => GSR,
      O => clear_GSR_OR
    );
  clk_count_1_OBUF_GTS_TRI_10 : X_TRI
    port map (
      I => clk_count_1_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_clk_count_1_OBUF_GTS_TRI_CTL,
      O => clk_count(1)
    );
  clk_count_0_OBUF_GTS_TRI_11 : X_TRI
    port map (
      I => clk_count_0_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_clk_count_0_OBUF_GTS_TRI_CTL,
      O => clk_count(0)
    );
  clk_307k_OBUF_GTS_TRI_12 : X_TRI
    port map (
      I => clk_307k_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_clk_307k_OBUF_GTS_TRI_CTL,
      O => clk_307k
    );
  clear_OBUF_GTS_TRI_13 : X_TRI
    port map (
      I => clear_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_clear_OBUF_GTS_TRI_CTL,
      O => clear
    );
  clk_count_2_OBUF_GTS_TRI_14 : X_TRI
    port map (
      I => clk_count_2_OBUF_GTS_TRI,
      CTL => NlwInverterSignal_clk_count_2_OBUF_GTS_TRI_CTL,
      O => clk_count(2)
    );
  NlwBlock_clk_gen_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_clk_gen_GND : X_ZERO
    port map (
      O => GND
    );
  NlwInverterBlock_clk_count_1_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_clk_count_1_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_clk_count_0_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_clk_count_0_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_clk_307k_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_clk_307k_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_clear_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_clear_OBUF_GTS_TRI_CTL
    );
  NlwInverterBlock_clk_count_2_OBUF_GTS_TRI_CTL : X_INV
    port map (
      I => GTS,
      O => NlwInverterSignal_clk_count_2_OBUF_GTS_TRI_CTL
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;