freedev_bt656_hw.tcl~

verilog代码读写SDRAM 不带仿真

# TCL File Generated by Component Editor on: 
# Fri Sep 07 09:11:37 CST 2007
# DO NOT MODIFY

set_source_file "freedev_bt656.v"
set_module "freedev_bt656"
set_module_description ""
set_module_property instantiateInSystemModule true
set_module_property version "1.0"
set_module_property group "User Logic"
set_module_property editable true
set_module_property simulationFiles {
  "bt656_detection.v"}

# Module parameters
add_parameter "IDLE" "integer" "6'b000001" ""
add_parameter "R_START0" "integer" "6'b000010" ""
add_parameter "R_START1" "integer" "6'b000100" ""
add_parameter "R_DATA" "integer" "6'b001000" ""
add_parameter "W_START" "integer" "6'b010000" ""
add_parameter "W_DATA" "integer" "6'b100000" ""

# Clock Interface global_signals_clock
add_clock_interface "global_signals_clock" 
set_interface_property "global_signals_clock" "externallyDriven" "false"
set_interface_property "global_signals_clock" "clockRateKnown" "false"
set_interface_property "global_signals_clock" "clockRate" "0"
# Ports in interface global_signals_clock
add_port_to_interface "global_signals_clock" "clk" "clk"
add_port_to_interface "global_signals_clock" "rst_n" "reset_n"

# Interface s
add_interface "s" "avalon" "slave" "global_signals_clock"
set_interface_property "s" "isNonVolatileStorage" "false"
set_interface_property "s" "burstOnBurstBoundariesOnly" "false"
set_interface_property "s" "transparentBridge" "false"
set_interface_property "s" "readLatency" "0"
set_interface_property "s" "readWaitStates" "1"
set_interface_property "s" "isFlash" "false"
set_interface_property "s" "holdTime" "0"
set_interface_property "s" "printableDevice" "false"
set_interface_property "s" "registerIncomingSignals" "false"
set_interface_property "s" "readWaitTime" "1"
set_interface_property "s" "setupTime" "0"
set_interface_property "s" "addressGroup" "0"
set_interface_property "s" "interleaveBursts" "false"
set_interface_property "s" "addressAlignment" "NATIVE"
set_interface_property "s" "isBigEndian" "false"
set_interface_property "s" "writeLatency" "0"
set_interface_property "s" "writeWaitTime" "1"
set_interface_property "s" "timingUnits" "Cycles"
set_interface_property "s" "minimumUninterruptedRunLength" "1"
set_interface_property "s" "registerOutgoingSignals" "false"
set_interface_property "s" "addressSpan" "16"
set_interface_property "s" "isMemoryDevice" "false"
set_interface_property "s" "linewrapBursts" "false"
set_interface_property "s" "alwaysBurstMaxBurst" "false"
set_interface_property "s" "writeWaitStates" "1"
set_interface_property "s" "maximumPendingReadTransactions" "0"
set_interface_property "s" "wellBehavedWaitrequest" "false"
# Ports in interface s
add_port_to_interface "s" "s_chipselect_n" "chipselect_n"
add_port_to_interface "s" "s_read_n" "read_n"
add_port_to_interface "s" "s_write_n" "write_n"
add_port_to_interface "s" "s_address" "address"
add_port_to_interface "s" "s_readdata" "readdata"
add_port_to_interface "s" "s_writedata" "writedata"

# IRQ Interface s_irq
add_interface "s_irq" "interrupt" "sender" "global_signals_clock"
set_interface_property "s_irq" "irqScheme" "NONE"
set_interface_property "s_irq" "associatedAddressablePoint" "s"
# Ports in interface s_irq
add_port_to_interface "s_irq" "s_irq" "irq"

# Wire Interface s_export
add_interface "s_export" "conduit" "output" "global_signals_clock"
# Ports in interface s_export
add_port_to_interface "s_export" "v_data" "export"
add_port_to_interface "s_export" "v_clk" "export"

# Interface avalon_master_0
add_interface "avalon_master_0" "avalon" "master" "global_signals_clock"
set_interface_property "avalon_master_0" "interleaveBursts" "false"
set_interface_property "avalon_master_0" "burstOnBurstBoundariesOnly" "false"
set_interface_property "avalon_master_0" "doStreamReads" "true"
set_interface_property "avalon_master_0" "isBigEndian" "false"
set_interface_property "avalon_master_0" "isWriteable" "false"
set_interface_property "avalon_master_0" "isAsynchronous" "false"
set_interface_property "avalon_master_0" "registerOutgoingSignals" "false"
set_interface_property "avalon_master_0" "maxAddressWidth" "32"
set_interface_property "avalon_master_0" "registerIncomingSignals" "false"
set_interface_property "avalon_master_0" "dBSBigEndian" "false"
set_interface_property "avalon_master_0" "alwaysBurstMaxBurst" "false"
set_interface_property "avalon_master_0" "linewrapBursts" "false"
set_interface_property "avalon_master_0" "addressGroup" "0"
set_interface_property "avalon_master_0" "doStreamWrites" "true"
set_interface_property "avalon_master_0" "isReadable" "false"
# Ports in interface avalon_master_0
add_port_to_interface "avalon_master_0" "m_waitrequest" "waitrequest"
add_port_to_interface "avalon_master_0" "m_address" "address"
add_port_to_interface "avalon_master_0" "m_read" "read"
add_port_to_interface "avalon_master_0" "m_readdata" "readdata"
add_port_to_interface "avalon_master_0" "m_write" "write"
add_port_to_interface "avalon_master_0" "m_writedata" "writedata"
add_port_to_interface "avalon_master_0" "m_byteenable" "byteenable"
add_port_to_interface "avalon_master_0" "m_burstcount" "burstcount"
add_port_to_interface "avalon_master_0" "m_readdatavalid" "readdatavalid"