vga_sys.sopc

verilog代码读写SDRAM 不带仿真

        <parameter valueString="14.0" name="TWR"/>
        <parameter valueString="0.0" name="initNOPDelay"/>
        <parameter valueString="15.625" name="refreshPeriod"/>
        <parameter valueString="5.5" name="TAC"/>
        <parameter valueString="9" name="columnWidth"/>
        <parameter valueString="4" name="numberOfBanks"/>
        <parameter valueString="2" name="numberOfChipSelects"/>
        <parameter valueString="false" name="pinsSharedViaTriState"/>
        <parameter valueString="20.0" name="TRCD"/>
        <parameter valueString="custom" name="model"/>
        <parameter valueString="67108864" name="size"/>
    </module>
    <module version="7.2" name="sys_clk_timer" kind="altera_avalon_timer">
        <parameter valueString="CUSTOM" name="timerPreset"/>
        <parameter valueString="20.0" name="period"/>
        <parameter valueString="false" name="resetOutput"/>
        <parameter valueString="MSEC" name="periodUnits"/>
        <parameter valueString="false" name="fixedPeriod"/>
        <parameter valueString="false" name="alwaysRun"/>
        <parameter valueString="false" name="timeoutPulseOutput"/>
        <parameter valueString="true" name="snapshot"/>
    </module>
    <module version="7.2" name="led_pio" kind="altera_avalon_pio">
        <parameter valueString="RISING" name="edgeType"/>
        <parameter valueString="4" name="width"/>
        <parameter valueString="Output" name="direction"/>
        <parameter valueString="LEVEL" name="irqType"/>
        <parameter valueString="false" name="captureEdge"/>
        <parameter valueString="false" name="simDoTestBenchWiring"/>
        <parameter valueString="false" name="generateIRQ"/>
        <parameter valueString="false" name="bitClearingEdgeCapReg"/>
        <parameter valueString="0" name="simDrivenValue"/>
    </module>
    <module version="7.2" name="tristate_bridge" kind="altera_avalon_tri_state_bridge">
        <parameter valueString="true" name="registerIncomingSignals"/>
    </module>
    <module version="7.2" name="cfi_flash" kind="altera_avalon_cfi_flash">
        <parameter valueString="16" name="dataWidth"/>
        <parameter name="sharedPorts">s1/address,s1/data,s1/read_n,s1/write_n</parameter>
        <parameter valueString="40" name="holdTime"/>
        <parameter valueString="40.0" name="actualSetupTime"/>
        <parameter valueString="160.0" name="actualWaitTime"/>
        <parameter valueString="40.0" name="actualHoldTime"/>
        <parameter valueString="CUSTOM" name="corePreset"/>
        <parameter valueString="NS" name="timingUnits"/>
        <parameter valueString="160" name="waitTime"/>
        <parameter valueString="40" name="setupTime"/>
        <parameter valueString="24" name="addressWidth"/>
    </module>
    <module version="1.0" name="freedev_vga_inst" kind="freedev_vga">
        <parameter valueString="" name="sharedPorts"/>
        <parameter valueString="4" name="R_START1"/>
        <parameter valueString="8" name="R_DATA"/>
        <parameter valueString="1" name="IDLE"/>
        <parameter valueString="2" name="R_START0"/>
    </module>
    <module version="1.0" name="freedev_sram_0" kind="freedev_sram">
        <parameter name="sharedPorts">avalon_tristate_slave_0/address,avalon_tristate_slave_0/data,avalon_tristate_slave_0/be</parameter>
        <parameter name="instancePTF">MODULE freedev_sram_0
{
   class = "freedev_sram";
   class_version = "1.0";
   SYSTEM_BUILDER_INFO 
   {
      Instantiate_In_System_Module = "0";
      Has_Clock = "0";
      Top_Level_Ports_Are_Enumerated = "1";
      Is_Enabled = "1";
      View 
      {
         MESSAGES 
         {
         }
      }
   }
   COMPONENT_BUILDER 
   {
      GLS_SETTINGS 
      {
      }
   }
   PORT_WIRING 
   {
   }
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_parameters 
      {
      }
   }
   SIMULATION 
   {
      DISPLAY 
      {
         SIGNAL x101
         {
            name = "freedev_sram/global_signals";
            format = "Divider";
         }
         SIGNAL x102
         {
            name = "freedev_sram/avalon_tristate_slave_0";
            format = "Divider";
         }
         SIGNAL x103
         {
            name = "address";
            radix = "hexadecimal";
         }
         SIGNAL x104
         {
            name = "data";
            radix = "hexadecimal";
         }
         SIGNAL x105
         {
            name = "be";
            radix = "hexadecimal";
         }
         SIGNAL x106
         {
            name = "oe";
         }
         SIGNAL x107
         {
            name = "we";
         }
         SIGNAL x108
         {
            name = "ce";
         }
      }
   }
   SLAVE avalon_tristate_slave_0
   {
      SYSTEM_BUILDER_INFO 
      {
         Bus_Type = "avalon_tristate";
         Address_Group = "1";
         Has_Clock = "0";
         Address_Width = "18";
         Address_Alignment = "dynamic";
         Data_Width = "16";
         Has_Base_Address = "1";
         Has_IRQ = "0";
         Setup_Time = "10ns";
         Hold_Time = "5ns";
         Read_Wait_States = "0ns";
         Write_Wait_States = "0ns";
         Read_Latency = "0";
         Maximum_Pending_Read_Transactions = "0";
         Active_CS_Through_Read_Latency = "0";
         Is_Printable_Device = "0";
         Is_Memory_Device = "1";
         Is_Readable = "1";
         Is_Writable = "1";
         Minimum_Uninterrupted_Run_Length = "1";
      }
      COMPONENT_BUILDER 
      {
         ATS_SETTINGS 
         {
            Setup_Value = "10";
            Read_Wait_Value = "0";
            Write_Wait_Value = "0";
            Hold_Value = "5";
            Timing_Units = "ns";
            Read_Latency_Value = "0";
            Minimum_Arbitration_Shares = "1";
            Active_CS_Through_Read_Latency = "0";
            Max_Pending_Read_Transactions_Value = "1";
            Address_Alignment = "dynamic";
            Is_Printable_Device = "0";
            Interleave_Bursts = "0";
            interface_name = "Avalon Tristate Slave";
            external_wait = "0";
            Is_Memory_Device = "1";
         }
      }
      PORT_WIRING 
      {
         PORT address
         {
            width = "18";
            width_expression = "";
            direction = "input";
            type = "address";
            is_shared = "1";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT data
         {
            width = "16";
            width_expression = "";
            direction = "inout";
            type = "data";
            is_shared = "1";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT be
         {
            width = "2";
            width_expression = "";
            direction = "input";
            type = "byteenable_n";
            is_shared = "1";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT oe
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "read_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT we
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "write_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT ce
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "chipselect_n";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
   }
}
</parameter>
    </module>
    <connection version="7.2" start="clk.clk" kind="clock" end="cpu.clk"/>
    <connection version="7.2" start="cpu.instruction_master" kind="avalon" end="cpu.jtag_debug_module">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02100800" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="cpu.jtag_debug_module">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02100800" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="jtag_uart.clk"/>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="jtag_uart.avalon_jtag_slave">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02101070" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="cpu.d_irq" kind="interrupt" end="jtag_uart.irq">
        <parameter valueString="0" name="irqNumber"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="sysid.clk"/>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="sysid.control_slave">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02101078" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="sdram.clk"/>
    <connection version="7.2" start="cpu.instruction_master" kind="avalon" end="sdram.s1">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x08000000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="sdram.s1">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x08000000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="sys_clk_timer.clk"/>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="sys_clk_timer.s1">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02101040" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="cpu.d_irq" kind="interrupt" end="sys_clk_timer.irq">
        <parameter valueString="1" name="irqNumber"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="led_pio.clk"/>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="led_pio.s1">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02101060" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="tristate_bridge.clk"/>
    <connection version="7.2" start="cpu.instruction_master" kind="avalon" end="tristate_bridge.avalon_slave">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x0000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="tristate_bridge.avalon_slave">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x0000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="cfi_flash.clk"/>
    <connection version="7.2" start="tristate_bridge.tristate_master" kind="avalon_tristate" end="cfi_flash.s1">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x0000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="clk.clk" kind="clock" end="freedev_vga_inst.clock"/>
    <connection version="7.2" start="cpu.data_master" kind="avalon" end="freedev_vga_inst.avalon_slave_0">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02101000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="cpu.d_irq" kind="interrupt" end="freedev_vga_inst.interrupt_sender">
        <parameter valueString="2" name="irqNumber"/>
    </connection>
    <connection version="7.2" start="freedev_vga_inst.avalon_master" kind="avalon" end="sdram.s1">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x08000000" name="baseAddress"/>
    </connection>
    <connection version="7.2" start="tristate_bridge.tristate_master" kind="avalon_tristate" end="freedev_sram_0.avalon_tristate_slave_0">
        <parameter valueString="1" name="arbitrationPriority"/>
        <parameter valueString="0x02080000" name="baseAddress"/>
    </connection>
</system>