📄 vga_sys.ptf
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SIGNAL ace
{
format = "Logic";
name = "M_pipe_flush_baddr";
radix = "hexadecimal";
}
SIGNAL acf
{
format = "Logic";
name = "A_ienable_reg";
radix = "hexadecimal";
}
SIGNAL acg
{
format = "Logic";
name = "A_status_reg_pie";
radix = "hexadecimal";
}
SIGNAL ach
{
format = "Logic";
name = "intr_req";
radix = "hexadecimal";
}
SIGNAL aci
{
format = "Logic";
name = "E_valid_prior_to_hbreak";
radix = "hexadecimal";
}
}
}
}
MODULE jtag_uart
{
SLAVE avalon_jtag_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT av_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dataavailable
{
type = "dataavailable";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
JTAG_Hub_Base_Id = "262254";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02101070";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x02101070";
Address_Group = "0";
}
}
class = "altera_avalon_jtag_uart";
class_version = "7.07";
iss_model_name = "altera_avalon_jtag_uart";
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
SIGNAL av_irq
{
name = "av_irq";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
Fix_Me_Up = "";
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
Instantiate_In_System_Module = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
<br>Read Depth: 64; Read IRQ Threshold: 8";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE sysid
{
SLAVE control_slave
{
PORT_WIRING
{
PORT clock
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "0";
}
PORT address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x02101078";
}
Base_Address = "0x02101078";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
}
class = "altera_avalon_sysid";
class_version = "7.07";
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
View
{
Settings_Summary = "System ID (at last Generate):<br> <b>032BCCBF</b> (unique ID tag) <br> <b>4733DA16</b> (timestamp: Fri Nov 9, 2007 @11:55 AM)";
MESSAGES
{
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
id = "53202111u";
timestamp = "1194580502u";
regenerate_values = "0";
MAKE
{
TARGET verifysysid
{
verifysysid
{
All_Depends_On = "0";
Command = "nios2-download $(JTAG_CABLE) --sidp=0x02101078 --id=53202111 --timestamp=1194580502";
Is_Phony = "1";
Target_File = "dummy_verifysysid_file";
}
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE sdram
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_addr
{
type = "address";
width = "25";
direction = "input";
Is_Enabled = "1";
}
PORT az_be_n
{
type = "byteenable_n";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT az_cs
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_data
{
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